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<p class="MsoNormal">Hi,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I have a question related to pre-RA scheduling and spill of registers.<o:p></o:p></p>
<p class="MsoNormal">I’m writing a backend for two operands instructions set, so FPU operations result have implicit destination.<o:p></o:p></p>
<p class="MsoNormal">For example, the result of FMUL_A_oo is implicitly the register FA_ROUTMUL.<o:p></o:p></p>
<p class="MsoNormal">I have defined FPUaROUTMULRegisterClass containing only FA_ROUTMUL.<o:p></o:p></p>
<p class="MsoNormal">During the instruction lowering, in order to avoid frequent spill out of FA_ROUTMUL, I systematically copy the result of FMUL_A_oo to a virtual register through a COPY_TO_REGCLASS.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal" style="text-autospace:none"><span style="font-size:10.0pt;font-family:Monospace;color:black">def : Pat<(fdiv f32:$OffsetA, f32:$OffsetB), (COPY_TO_REGCLASS (FDIV_A_oo FPUaOffsetOperand:$OffsetA,FPUaOffsetOperand:$OffsetB),FPUaOffsetClass)>;</span><span style="font-size:10.0pt;font-family:Monospace"><o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">The instruction lowering goes as expected all instances of FMUL_A_oo are followed by a COPY, freeing the usage of FPUaROUTMULRegisterClass.<o:p></o:p></p>
<p class="MsoNormal">These COPY are at positions 64B and 112B in the example below. So far, so good.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">My problem arise in some pre-RA instruction scheduling optimization moving these COPY at later positions 104B and 112B.<o:p></o:p></p>
<p class="MsoNormal">The new code sequence leaves two FMUL_A_oo without COPY. So this requires 2 registers from FPUaROUTMULRegisterClass (which only includes FA_ROUTMUL).<o:p></o:p></p>
<p class="MsoNormal">So spill out need to be inserted where I tried to avoid it by inserting the COPY. :-/<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">This ‘handleMove’ is generated by LiveIntervalAnalysis, but I don’t understand why it is generated and how to avoid this counterproductive optimization.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">TIA, Dominique Torette.<o:p></o:p></p>
<p class="MsoNormal"><o:p></o:p></p>
<p class="MsoNormal"># *** IR Dump After MachineFunction Printer ***:<o:p></o:p></p>
<p class="MsoNormal"># Machine code for function addproddivConst: Post SSA<o:p></o:p></p>
<p class="MsoNormal">Function Live Ins: %FA_ROFF1 in %vreg0<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">0B BB#0: derived from LLVM BB %entry<o:p></o:p></p>
<p class="MsoNormal"> Live Ins: %FA_ROFF1<o:p></o:p></p>
<p class="MsoNormal">16B %vreg0<def> = COPY %FA_ROFF1; FPUaOffsetClass:%vreg0<o:p></o:p></p>
<p class="MsoNormal">32B %vreg2<def> = MOVSUTO_A_iSLo 1077936128; FPUaOffsetClass:%vreg2<o:p></o:p></p>
<p class="MsoNormal">48B %vreg3<def> = FMUL_A_oo %vreg0, %vreg2, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%vreg3 FPUaOffsetClass:%vreg0,%vreg2<o:p></o:p></p>
<p class="MsoNormal">64B %vreg4<def> = COPY %vreg3; FPUaOffsetClass:%vreg4 FPUaROUTMULRegisterClass:%vreg3<o:p></o:p></p>
<p class="MsoNormal">80B %vreg5<def> = MOVSUTO_A_iSLo 1056964608; FPUaOffsetClass:%vreg5<o:p></o:p></p>
<p class="MsoNormal">96B %vreg6<def> = FMUL_A_oo %vreg0, %vreg5, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%vreg6 FPUaOffsetClass:%vreg0,%vreg5<o:p></o:p></p>
<p class="MsoNormal">112B %vreg7<def> = COPY %vreg6; FPUaOffsetClass:%vreg7 FPUaROUTMULRegisterClass:%vreg6<o:p></o:p></p>
<p class="MsoNormal">128B %vreg8<def> = FADD_A_oo %vreg4, %vreg7, %RFLAGA<imp-def,dead>; FPUaROUTADDRegisterClass:%vreg8 FPUaOffsetClass:%vreg4,%vreg7<o:p></o:p></p>
<p class="MsoNormal">144B %FA_ROFF0<def> = COPY %vreg8; FPUaROUTADDRegisterClass:%vreg8<o:p></o:p></p>
<p class="MsoNormal">176B MOVSUTO_SU_os_rpc %SU_ROFF0<kill>, %RPC<imp-def,dead><o:p></o:p></p>
<p class="MsoNormal">192B NOP<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"># End machine code for function addproddivConst.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">handleMove 64B -> 104B: %vreg4<def> = COPY %vreg3; FPUaOffsetClass:%vreg4 FPUaROUTMULRegisterClass:%vreg3<o:p></o:p></p>
<p class="MsoNormal"> %vreg4: [64r,128r:0) 0@64r<o:p></o:p></p>
<p class="MsoNormal"> --> [104r,128r:0) 0@104r<o:p></o:p></p>
<p class="MsoNormal"> %vreg3: [48r,64r:0) 0@48r<o:p></o:p></p>
<p class="MsoNormal"> --> [48r,104r:0) 0@48r<o:p></o:p></p>
<p class="MsoNormal"># *** IR Dump After Machine Instruction Scheduler ***:<o:p></o:p></p>
<p class="MsoNormal"># Machine code for function addproddivConst: Post SSA<o:p></o:p></p>
<p class="MsoNormal">Function Live Ins: %FA_ROFF1 in %vreg0<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">0B BB#0: derived from LLVM BB %entry<o:p></o:p></p>
<p class="MsoNormal"> Live Ins: %FA_ROFF1<o:p></o:p></p>
<p class="MsoNormal">16B %vreg0<def> = COPY %FA_ROFF1; FPUaOffsetClass:%vreg0<o:p></o:p></p>
<p class="MsoNormal">32B %vreg2<def> = MOVSUTO_A_iSLo 1077936128; FPUaOffsetClass:%vreg2<o:p></o:p></p>
<p class="MsoNormal">48B %vreg3<def> = FMUL_A_oo %vreg0, %vreg2, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%vreg3 FPUaOffsetClass:%vreg0,%vreg2<o:p></o:p></p>
<p class="MsoNormal">80B %vreg5<def> = MOVSUTO_A_iSLo 1056964608; FPUaOffsetClass:%vreg5<o:p></o:p></p>
<p class="MsoNormal">96B %vreg6<def> = FMUL_A_oo %vreg0, %vreg5, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%vreg6 FPUaOffsetClass:%vreg0,%vreg5<o:p></o:p></p>
<p class="MsoNormal">104B %vreg4<def> = COPY %vreg3; FPUaOffsetClass:%vreg4 FPUaROUTMULRegisterClass:%vreg3<o:p></o:p></p>
<p class="MsoNormal">112B %vreg7<def> = COPY %vreg6; FPUaOffsetClass:%vreg7 FPUaROUTMULRegisterClass:%vreg6<o:p></o:p></p>
<p class="MsoNormal">128B %vreg8<def> = FADD_A_oo %vreg4, %vreg7, %RFLAGA<imp-def,dead>; FPUaROUTADDRegisterClass:%vreg8 FPUaOffsetClass:%vreg4,%vreg7<o:p></o:p></p>
<p class="MsoNormal">144B %FA_ROFF0<def> = COPY %vreg8; FPUaROUTADDRegisterClass:%vreg8<o:p></o:p></p>
<p class="MsoNormal">176B MOVSUTO_SU_os_rpc %SU_ROFF0<kill>, %RPC<imp-def,dead><o:p></o:p></p>
<p class="MsoNormal">192B NOP<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"># End machine code for function addproddivConst.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal" style="margin-bottom:12.0pt"><span style="font-size:12.0pt;font-family:"Times New Roman","serif""><br>
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<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Times New Roman","serif""><img width="536" height="49" id="_x0000_i1025" src="http://www.spacebel.be/wp-content/uploads/2018/02/image-sign-sbp30y-1.jpg" alt="http://www.spacebel.be/wp-content/uploads/2018/02/image-sign-sbp30y-1.jpg"></span><span style="font-size:12.0pt;font-family:"Times New Roman","serif""><o:p></o:p></span></p>
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<p class="MsoNormal" align="center" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;text-align:center">
<b><span lang="FR-BE" style="font-size:10.0pt">Dominique Torette</span></b><span lang="FR-BE" style="font-size:10.0pt">
<br>
System Architect<br>
Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur <br>
Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 <br>
</span><span style="font-size:10.0pt"><a href="http://www.spacebel.be/"><span lang="FR-BE" style="color:blue">www.spacebel.be</span></a></span><span lang="FR-BE" style="font-size:12.0pt;font-family:"Times New Roman","serif""><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="FR-BE"><o:p> </o:p></span></p>
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