<div dir="ltr">Hi Dominque,<div><br></div><div>Not commenting on the scheduling part as I don't know how the register pressure tracking is done there.</div><div>Unless you constrain your copies to stay next to the MUL_A (e.g., using a bundle), there is a non-zero chance that something is going to mess with them.</div><div><br></div><div>That said, the splitting mechanism should just insert the desired copies to avoid spilling for you.</div><div>Could you check why this is not happening? (-debug-only=regalloc and check why it spills or why the splitting failed.)</div><div><br></div><div>One possible problem is that you don't have a bigger regclass that contains <span style="font-size:12.8px">FPUaROUTMULRegisterClass, that could be used when relaxing the constraint with splitting.</span></div><div><span style="font-size:12.8px"><br></span></div><div><span style="font-size:12.8px">Cheers,</span></div><div><span style="font-size:12.8px">-Quentin</span></div><div><span style="color:rgb(34,34,34);font-family:arial,sans-serif;font-size:12.8px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;letter-spacing:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline"><span style="color:rgb(34,34,34);font-family:arial,sans-serif;font-size:12.8px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;letter-spacing:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline"></span></span></div></div><div class="gmail_extra"><br><div class="gmail_quote">2018-04-23 1:50 GMT-07:00 Dominique Torette via llvm-dev <span dir="ltr"><<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>></span>:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
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<p class="MsoNormal">Hi,<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">I have a question related to pre-RA scheduling and spill of registers.<u></u><u></u></p>
<p class="MsoNormal">I’m writing a backend for two operands instructions set, so FPU operations result have implicit destination.<u></u><u></u></p>
<p class="MsoNormal">For example, the result of FMUL_A_oo is implicitly the register FA_ROUTMUL.<u></u><u></u></p>
<p class="MsoNormal">I have defined FPUaROUTMULRegisterClass containing only FA_ROUTMUL.<u></u><u></u></p>
<p class="MsoNormal">During the instruction lowering, in order to avoid frequent spill out of FA_ROUTMUL, I systematically copy the result of FMUL_A_oo to a virtual register through a COPY_TO_REGCLASS.<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal" style="text-autospace:none"><span style="font-size:10.0pt;font-family:Monospace;color:black">def : Pat<(fdiv f32:$OffsetA, f32:$OffsetB), (COPY_TO_REGCLASS (FDIV_A_oo FPUaOffsetOperand:$OffsetA,<wbr>FPUaOffsetOperand:$OffsetB),<wbr>FPUaOffsetClass)>;</span><span style="font-size:10.0pt;font-family:Monospace"><u></u><u></u></span></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">The instruction lowering goes as expected all instances of FMUL_A_oo are followed by a COPY, freeing the usage of FPUaROUTMULRegisterClass.<u></u><u></u></p>
<p class="MsoNormal">These COPY are at positions 64B and 112B in the example below. So far, so good.<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">My problem arise in some pre-RA instruction scheduling optimization moving these COPY at later positions 104B and 112B.<u></u><u></u></p>
<p class="MsoNormal">The new code sequence leaves two FMUL_A_oo without COPY. So this requires 2 registers from FPUaROUTMULRegisterClass (which only includes FA_ROUTMUL).<u></u><u></u></p>
<p class="MsoNormal">So spill out need to be inserted where I tried to avoid it by inserting the COPY. :-/<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">This ‘handleMove’ is generated by LiveIntervalAnalysis, but I don’t understand why it is generated and how to avoid this counterproductive optimization.<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">TIA, Dominique Torette.<u></u><u></u></p>
<p class="MsoNormal"><u></u><u></u></p>
<p class="MsoNormal"># *** IR Dump After MachineFunction Printer ***:<u></u><u></u></p>
<p class="MsoNormal"># Machine code for function addproddivConst: Post SSA<u></u><u></u></p>
<p class="MsoNormal">Function Live Ins: %FA_ROFF1 in %vreg0<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">0B BB#0: derived from LLVM BB %entry<u></u><u></u></p>
<p class="MsoNormal"> Live Ins: %FA_ROFF1<u></u><u></u></p>
<p class="MsoNormal">16B %vreg0<def> = COPY %FA_ROFF1; FPUaOffsetClass:%vreg0<u></u><u></u></p>
<p class="MsoNormal">32B %vreg2<def> = MOVSUTO_A_iSLo 1077936128; FPUaOffsetClass:%vreg2<u></u><u></u></p>
<p class="MsoNormal">48B %vreg3<def> = FMUL_A_oo %vreg0, %vreg2, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%<wbr>vreg3 FPUaOffsetClass:%vreg0,%vreg2<u></u><u></u></p>
<p class="MsoNormal">64B %vreg4<def> = COPY %vreg3; FPUaOffsetClass:%vreg4 FPUaROUTMULRegisterClass:%<wbr>vreg3<u></u><u></u></p>
<p class="MsoNormal">80B %vreg5<def> = MOVSUTO_A_iSLo 1056964608; FPUaOffsetClass:%vreg5<u></u><u></u></p>
<p class="MsoNormal">96B %vreg6<def> = FMUL_A_oo %vreg0, %vreg5, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%<wbr>vreg6 FPUaOffsetClass:%vreg0,%vreg5<u></u><u></u></p>
<p class="MsoNormal">112B %vreg7<def> = COPY %vreg6; FPUaOffsetClass:%vreg7 FPUaROUTMULRegisterClass:%<wbr>vreg6<u></u><u></u></p>
<p class="MsoNormal">128B %vreg8<def> = FADD_A_oo %vreg4, %vreg7, %RFLAGA<imp-def,dead>; FPUaROUTADDRegisterClass:%<wbr>vreg8 FPUaOffsetClass:%vreg4,%vreg7<u></u><u></u></p>
<p class="MsoNormal">144B %FA_ROFF0<def> = COPY %vreg8; FPUaROUTADDRegisterClass:%<wbr>vreg8<u></u><u></u></p>
<p class="MsoNormal">176B MOVSUTO_SU_os_rpc %SU_ROFF0<kill>, %RPC<imp-def,dead><u></u><u></u></p>
<p class="MsoNormal">192B NOP<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal"># End machine code for function addproddivConst.<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">handleMove 64B -> 104B: %vreg4<def> = COPY %vreg3; FPUaOffsetClass:%vreg4 FPUaROUTMULRegisterClass:%<wbr>vreg3<u></u><u></u></p>
<p class="MsoNormal"> %vreg4: [64r,128r:0) 0@64r<u></u><u></u></p>
<p class="MsoNormal"> --> [104r,128r:0) 0@104r<u></u><u></u></p>
<p class="MsoNormal"> %vreg3: [48r,64r:0) 0@48r<u></u><u></u></p>
<p class="MsoNormal"> --> [48r,104r:0) 0@48r<u></u><u></u></p>
<p class="MsoNormal"># *** IR Dump After Machine Instruction Scheduler ***:<u></u><u></u></p>
<p class="MsoNormal"># Machine code for function addproddivConst: Post SSA<u></u><u></u></p>
<p class="MsoNormal">Function Live Ins: %FA_ROFF1 in %vreg0<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">0B BB#0: derived from LLVM BB %entry<u></u><u></u></p>
<p class="MsoNormal"> Live Ins: %FA_ROFF1<u></u><u></u></p>
<p class="MsoNormal">16B %vreg0<def> = COPY %FA_ROFF1; FPUaOffsetClass:%vreg0<u></u><u></u></p>
<p class="MsoNormal">32B %vreg2<def> = MOVSUTO_A_iSLo 1077936128; FPUaOffsetClass:%vreg2<u></u><u></u></p>
<p class="MsoNormal">48B %vreg3<def> = FMUL_A_oo %vreg0, %vreg2, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%<wbr>vreg3 FPUaOffsetClass:%vreg0,%vreg2<u></u><u></u></p>
<p class="MsoNormal">80B %vreg5<def> = MOVSUTO_A_iSLo 1056964608; FPUaOffsetClass:%vreg5<u></u><u></u></p>
<p class="MsoNormal">96B %vreg6<def> = FMUL_A_oo %vreg0, %vreg5, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%<wbr>vreg6 FPUaOffsetClass:%vreg0,%vreg5<u></u><u></u></p>
<p class="MsoNormal">104B %vreg4<def> = COPY %vreg3; FPUaOffsetClass:%vreg4 FPUaROUTMULRegisterClass:%<wbr>vreg3<u></u><u></u></p>
<p class="MsoNormal">112B %vreg7<def> = COPY %vreg6; FPUaOffsetClass:%vreg7 FPUaROUTMULRegisterClass:%<wbr>vreg6<u></u><u></u></p>
<p class="MsoNormal">128B %vreg8<def> = FADD_A_oo %vreg4, %vreg7, %RFLAGA<imp-def,dead>; FPUaROUTADDRegisterClass:%<wbr>vreg8 FPUaOffsetClass:%vreg4,%vreg7<u></u><u></u></p>
<p class="MsoNormal">144B %FA_ROFF0<def> = COPY %vreg8; FPUaROUTADDRegisterClass:%<wbr>vreg8<u></u><u></u></p>
<p class="MsoNormal">176B MOVSUTO_SU_os_rpc %SU_ROFF0<kill>, %RPC<imp-def,dead><u></u><u></u></p>
<p class="MsoNormal">192B NOP<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal"># End machine code for function addproddivConst.<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
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<b><span lang="FR-BE" style="font-size:10.0pt">Dominique Torette</span></b><span lang="FR-BE" style="font-size:10.0pt">
<br>
System Architect<br>
Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur <br>
Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 <br>
</span><span style="font-size:10.0pt"><a href="http://www.spacebel.be/" target="_blank"><span lang="FR-BE" style="color:blue">www.spacebel.be</span></a></span><span lang="FR-BE" style="font-size:12.0pt;font-family:"Times New Roman","serif""><u></u><u></u></span></p>
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<p class="MsoNormal"><span lang="FR-BE"><u></u> <u></u></span></p>
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