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<p class="MsoNormal">Hi,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I’ve some problems/questions while implementing the BUILD_VECTOR primitive for a SIMD microcontroller…<o:p></o:p></p>
<p class="MsoNormal">This microcontroller has two FPU units: UnitA and UnitB.<o:p></o:p></p>
<p class="MsoNormal">UnitA has a bank of 512 registers named RegisterA_0 .. RegisterA_511.<o:p></o:p></p>
<p class="MsoNormal">UnitB has a bank of 512 registers named RegisterB_0 .. RegisterB_511.<o:p></o:p></p>
<p class="MsoNormal">The FPU instruction format has a 2 bits operand indicating which units are involved: none, only UnitA, only UnitB, and the SIMD version UnitA and UnitB.<o:p></o:p></p>
<p class="MsoNormal">The SIMD version of a FPU instruction operates on registers with the same ID of both banks.<o:p></o:p></p>
<p class="MsoNormal">For examples:<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><span style="font-family:"Courier New""> FADD A R1, R2; // => ACC_A = RegisterA_1 + RegisterA_1<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Courier New""> FADD B R5, R6; // => ACC_B = RegisterB_5 + RegisterB_6<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Courier New""> FADD AB R7, R8; // => ACC_A = RegisterA_7 + RegisterA_8 and ACC_B = RegisterB_7 + RegisterB_8<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">From a machine registers definition point of view, I’ve first defined the 512 UnitA registers in a RegisterClass RegClassA and the 512 UnitB registers in a RegisterClass RegClassB.<o:p></o:p></p>
<p class="MsoNormal">In order to defined registers operands for the SIMD version of FPU instructions, I’ve then defined 512 registers in a RegisterClass RegClassAB.<o:p></o:p></p>
<p class="MsoNormal">The registers from RegClassAB overlap the one the ones of RegClassA and RegClassB in this way RegClassAB.R1 has two subregisters: RegClassA.R1 and RegClassB.R1.<o:p></o:p></p>
<p class="MsoNormal">So far, so good. I can generated code for math expression taking advantage of SIMD FPU!<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">My problem is on the implementation of the BUILD_VECTOR that should build RegClassAB register from a pair of RegClassA/RegClassB registers or constants.<o:p></o:p></p>
<p class="MsoNormal">For this purpose, I only have a MOV instruction operating either on UnitA or UnitB.<o:p></o:p></p>
<p class="MsoNormal">So from the BUILD_VECTOR, I have to generate two MOV instructions, one for the UnitA and UnitB.
<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Assuming that %vreg3 (of class RegClassAB) will be allocated to R22, <span style="font-family:"Courier New"">%vreg3<def> = BUILD_VECTOR 2.7172, 3.1416</span> should be lowered into:<o:p></o:p></p>
<p class="MsoNormal" align="center" style="text-align:center"><o:p> </o:p></p>
<p class="MsoNormal"><span style="font-family:"Courier New""> MOV A 2.7172, R22 ; // RegisterA_22 = 2.7172<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Courier New""> MOV B 3.1416, R22; // RegisterB_22 = 3.1416<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Generating the two instruction could be easily done by custom inserter at end of Instruction Selection.<o:p></o:p></p>
<p class="MsoNormal">It is understood that the MachineRegisterInfo has all the information about the sub-registers overlapping. <o:p></o:p></p>
<p class="MsoNormal"> <o:p></o:p></p>
<p class="MsoNormal">But the problem is have to map (before registers allocation) _<i>one Virtual Register</i>_ of RegClassAB into the _<i>two overlapping physical sub-registers</i>_ !<br>
<br>
<o:p></o:p></p>
<p class="MsoNormal">Has someone an idea to properly lowering and allocating registers to BUILD_VECTOR, considering my SIMD registers definition and my instructions set?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Thanks in advance, comments are welcome. Dominique Torette.<o:p></o:p></p>
<p class="MsoNormal"><br>
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<o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Times New Roman","serif""><img width="536" height="49" id="_x0000_i1025" src="http://www.spacebel.be/wp-content/uploads/2018/02/image-sign-sbp30y-1.jpg" alt="http://www.spacebel.be/wp-content/uploads/2018/02/image-sign-sbp30y-1.jpg"></span><span lang="FR-BE" style="font-size:12.0pt;font-family:"Times New Roman","serif""><o:p></o:p></span></p>
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<b><span lang="FR-BE" style="font-size:10.0pt">Dominique Torette</span></b><span lang="FR-BE" style="font-size:10.0pt">
<br>
System Architect<br>
Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur <br>
Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20 <br>
</span><span style="font-size:10.0pt"><a href="http://www.spacebel.be/"><span lang="FR-BE" style="color:blue">www.spacebel.be</span></a></span><span lang="FR-BE" style="font-size:12.0pt;font-family:"Times New Roman","serif""><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="FR-BE"><o:p> </o:p></span></p>
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