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<p class="MsoNormal">Hi, <o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I’m writing a backend for a proprietary microcontroller.<o:p></o:p></p>
<p class="MsoNormal">I’m facing a limitation related to Live Interval Analysis. <o:p>
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<p class="MsoNormal">Some FPU instructions, most notably the FDIV, requires a few cycles to complete.<o:p></o:p></p>
<p class="MsoNormal">There is a pipeline and, during the execution of the FDIV, others instructions could be executed in parallel, provided they don’t use the same registers.<o:p></o:p></p>
<p class="MsoNormal">This pipeline has been modeled for the instruction scheduling through SchedMachineModel and ProcessorItineraries in .td file.<o:p></o:p></p>
<p class="MsoNormal">My problem is that the Live Interval Analysis seems to be over optimistic. It consider that the interval is closed when the FPU instruction start, not when it is completed.<o:p></o:p></p>
<p class="MsoNormal">With such analysis it reallocate a physical register to early, while still used by the FPU instruction, which compromises the FPU result.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Is there a mechanism (.td scheduling model or C++ hook) to extend the live analysis range in order to cover the pipeline execution?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Thanks in advance, Dominique Torette.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Times New Roman","serif""><img width="536" height="49" id="_x0000_i1025" src="http://www.spacebel.be/wp-content/uploads/2018/02/image-sign-sbp30y-1.jpg" alt="http://www.spacebel.be/wp-content/uploads/2018/02/image-sign-sbp30y-1.jpg"></span><span style="font-size:12.0pt;font-family:"Times New Roman","serif""><o:p></o:p></span></p>
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<p class="MsoNormal" align="center" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;text-align:center">
<b><span style="font-size:10.0pt">Dominique Torette</span></b><span style="font-size:10.0pt">
<br>
System Architect<br>
Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur <br>
Tel: +32 (0) 4 </span><span lang="FR-BE" style="font-size:10.0pt">361 81 11 - Fax: +32 (0) 4 361 81 20
<br>
</span><span style="font-size:10.0pt"><a href="http://www.spacebel.be/"><span lang="FR-BE" style="color:blue">www.spacebel.be</span></a></span><span lang="FR-BE" style="font-size:12.0pt;font-family:"Times New Roman","serif""><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="FR-BE"><o:p> </o:p></span></p>
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