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<p>Thank you for your help Tom<br>
</p>
you are totally right with the registers but the command you suggest
also doesn't work.<br>
After some research I found the following thread on the mailing
list: <a moz-do-not-send="true"
href="http://lists.llvm.org/pipermail/llvm-dev/2017-February/110086.html">http://lists.llvm.org/pipermail/llvm-dev/2017-February/110086.html</a><br>
With your help and the information about the condition codes I was
able to resolve the error:<br>
<blockquote> BuildMI(BB, BB.end(), DL,
TII->get(ARM::tCMPi8)).addReg(ARM::R0).addImm(1).add(predOps(ARMCC::AL);<br>
</blockquote>
But how do I know how many and which condition codes each
instruction needs? [MOVi takes 3 operands relating to the condition
code (all after the immediate)]<br>
There is no info about that in the ARMInstrThumb.td file.<br>
<br>
-Julius<br>
<br>
<div class="moz-cite-prefix">On 03/23/2018 12:18 AM, Tom Stellard
wrote:<br>
</div>
<blockquote type="cite"
cite="mid:be9b79e5-7b1a-3c43-7bcd-b7978d728920@redhat.com">
<pre wrap="">On 03/22/2018 09:29 AM, Julius Hiller via llvm-dev wrote:
</pre>
<blockquote type="cite">
<pre wrap="">Hello everyone,
I'm working on a MachineFunctionPass that inserts a list of instructions into an Module so a later Pass can work on them.
To do so I load a dummy .ll file created from a main stub, create the needed function stubs (ModulePass), insert Blocks and create instructions using BuildMI.
I started with branch instructions:
const TargetMachine &TM = MF.getTarget();
const MCInstrInfo *TII = TM.getMCInstrInfo();
DebugLoc DL;
BuildMI(BB, BB.end(), DL, TII->get(ARM::B)).addMBB(trgBlock);
these are working fine.
When creating an compare instruction like cmp r0, 1 with:
BuildMI(BB, BB.end(), DL, TII->get(ARM::tCMPi8),0).addImm(1);
I get the following error:
.../include/llvm/MC/MCInst.h:81: int64_t llvm::MCOperand::getImm() const: Assertion `isImm() && "This is not an immediate"' failed.
</pre>
</blockquote>
<pre wrap="">According to ARMInstrThumb.td, tCMPi8's source arguments are reg, imm and
there is no explicit destination register, so what you want is:
BuildMI(BB, BB.end(), DL, TII->get(ARM::tCMPi8)).addReg(ARM::R0).addImm(1);
-Tom
</pre>
<blockquote type="cite">
<pre wrap="">Which even after hours I can't make sense why the operand kind is wrong.
Another thing I noticed is that using ARM::tB results in the following error:
.../include/llvm/ADT/SmallVector.h:154: const T& llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::operator[](llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::size_type) const [with T = llvm::MCOperand; <template-parameter-1-2> = void; llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::const_reference = const llvm::MCOperand&; llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::size_type = long unsigned int]: Assertion `idx < size()' failed.
The architecture is ARMv6-m, I am using llvm 7, the dummy.ll was created with llvm 3.9
Hope to find some help here, best regards
Julius Hiller
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</pre>
</blockquote>
</blockquote>
<br>
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