<div dir="ltr">Here's a couple examples for mapping an intrinsic to an X86 instruction from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can find others.<div><br></div><div><div>let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in</div><div>def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),</div><div> "clflushopt\t$src", [(int_x86_clflushopt addr:$src)],</div><div> IIC_SSE_PREFETCH>, PD;</div><div><br></div><div>let Predicates = [HasCLWB], SchedRW = [WriteLoad] in</div><div>def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src",</div><div> [(int_x86_clwb addr:$src)], IIC_SSE_PREFETCH>, PD;</div></div><div><br></div><div>The encoding information for the binary output is buried in these definitions too. If you tell me what opcode you've chosen I can tell you what the right things are to get the binary output.</div><div><br></div></div><div class="gmail_extra"><br clear="all"><div><div class="gmail_signature" data-smartmail="gmail_signature">~Craig</div></div>
<br><div class="gmail_quote">On Sun, Mar 18, 2018 at 3:22 PM, Gus Smith via llvm-dev <span dir="ltr"><<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div class="gmail_default" style="font-family:arial,helvetica,sans-serif;color:rgb(0,0,0)">Hello all. LLVM newbie here. If anything seems glaringly wrong with my use of LLVM, that's probably why.</div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif;color:rgb(0,0,0)"><br></div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif;color:rgb(0,0,0)">Here's what I'm trying to do. I have modified the gem5 simulator to accept a "new" x86 instruction. I've done this by just reserving the opcode in gem5's ISA specification, just as all other instructions are specified.</div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif;color:rgb(0,0,0)"><br></div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif;color:rgb(0,0,0)">I'm trying to get an LLVM backend to generate this opcode during code generation. My current plan is:</div><div class="gmail_default"><ol><li><font color="#000000" face="arial, helvetica, sans-serif">During an LLVM pass, I'll detect a series of instructions which can be replaced with this new instruction. (The new instruction is a "cache compute" instruction -- in my passes, I replace a series of loads, operations, and stores with this single instruction.) This step is complete.<br></font></li><li><font color="#000000" face="arial, helvetica, sans-serif">I replace the series of instructions with an intrinsic. I have added an intrinsic using the instructions <a href="https://llvm.org/docs/ExtendingLLVM.html#adding-a-new-intrinsic-function" target="_blank">here</a>. This step is complete.</font></li><li><font color="#000000" face="arial, helvetica, sans-serif">During code generation, the intrinsic should be converted to this reserved opcode. This is where I'm stuck.</font></li></ol><div><font color="#000000" face="arial, helvetica, sans-serif">I'm stuck on step 3. I have two main questions that should unblock me:</font></div><div><font color="#000000" face="arial, helvetica, sans-serif"><br></font></div><div><font color="#000000" face="arial, helvetica, sans-serif">Question 1: where is the code that maps from intrinsics to instructions? The link above states: </font></div><div><font color="#000000" face="arial, helvetica, sans-serif"><br></font></div><div><font color="#000000" face="arial, helvetica, sans-serif">"Add support to the .td file for the target(s) of your choice in lib/Target/*/*.td. </font><span style="color:rgb(0,0,0);font-family:arial,helvetica,sans-serif">This is usually a matter of adding a pattern to the .td file that matches the intrinsic, though it may obviously require adding the instructions you want to generate as well. There are lots of examples in the PowerPC and X86 backend to follow." </span></div><div><span style="color:rgb(0,0,0);font-family:arial,helvetica,sans-serif"><br></span></div><div><span style="color:rgb(0,0,0);font-family:arial,helvetica,sans-serif">However, looking through these examples isn't illuminating anything for me. Any more documentation or high-level explanation on this subject would be really helpful. I have read something about "lowering" of intrinsics; not sure if that's relevant.</span></div><div><span style="color:rgb(0,0,0);font-family:arial,helvetica,sans-serif"><br></span></div><div><span style="color:rgb(0,0,0);font-family:arial,helvetica,sans-serif">Question 2: will I be able to generate this opcode directly from the intrinsic, or will I have to add the opcode as an LLVM IR instruction and specify how it gets compiled? I can imagine two options: </span></div><div><font color="#000000" face="arial, helvetica, sans-serif">option 1: I can define a "translation" from intrinsic straight to an x86 opcode.</font></div><div><font color="#000000" face="arial, helvetica, sans-serif">option 2: I can define a "translation" (perhaps in a .td file? I think that's what they're used for) which translates my intrinsic into a new instruction, and then I can define another translation which will map the new instruction to my opcode during code gen. If this is the case, I'm not sure there's any point to having an intrinsic; I should just add a new instruction instead.</font></div><div><font color="#000000" face="arial, helvetica, sans-serif"><br></font></div><div><font color="#000000" face="arial, helvetica, sans-serif">Hoping someone can help! As you can tell, I'm a little lost...the documentation for LLVM is great, but it's a little above my level right now :)</font></div><div><font color="#000000" face="arial, helvetica, sans-serif"><br></font></div><div><font color="#000000" face="arial, helvetica, sans-serif">Gus Smith, PSU</font></div><div><br></div></div></div>
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