<html><head><meta http-equiv="Content-Type" content="text/html; charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><br class=""><div><br class=""><blockquote type="cite" class=""><div class="">On Mar 2, 2018, at 9:30 AM, Andrew Trick <<a href="mailto:atrick@apple.com" class="">atrick@apple.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><meta http-equiv="Content-Type" content="text/html; charset=utf-8" class=""><div style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class="">+Matthias<br class=""><div class=""><br class=""><blockquote type="cite" class=""><div class="">On Mar 2, 2018, at 6:42 AM, Andrea Di Biagio <<a href="mailto:andrea.dibiagio@gmail.com" class="">andrea.dibiagio@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class=""><div dir="ltr" class=""><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-style: solid; border-left-color: rgb(204, 204, 204); padding-left: 1ex;"><div style="word-wrap: break-word; line-break: after-white-space;" class=""><div class=""><blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; text-decoration: none;" class=""><div class=""><div dir="ltr" class=""><span class="">Known limitations on X86 processors<br class="">------------------------------<wbr class="">-----<br class=""><br class="">1) Partial register updates versus full register updates.<br class=""></span><snip><br class=""></div></div></blockquote><div style="caret-color: rgb(0, 0, 0); font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; text-decoration: none;" class=""><br class=""></div><span style="caret-color: rgb(0, 0, 0); font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; text-decoration: none; float: none; display: inline !important;" class="">MachineOperand handles this. You just need to create the machine instrs.</span></div></div></blockquote><div class=""><br class=""></div><div class="">Interesting. I couldn't find how to do it. It would be great if somebody helps me on this.</div></div></div></div></div></div></blockquote></div><div class=""><br class=""></div><div class="">I was thinking of APIs like MachineOperand::readsReg().</div><div class=""><br class=""></div>I guess if you’re only asking whether an instruction zeros the upper part of the register, that information *should* be available from MCInstr/MCRegisterInfo, but I’m not very familiar with the API.</div></div></blockquote><div><br class=""></div><div>I don’t think we have this information in an explicit form today:</div><div><br class=""></div><div>- It’s usually not a correctness problem because we cannot really address the upper register parts independently on those targets.</div><div>- We work around some ISEL shortcomings via `SUBREG_TO_REG` (see TargetOpcode.def) which I consider a nasty hack as stating assumptions about the predecessor node violates the referential transparency that you would expect from SSA.</div><div>- Coalescing/regalloc is using `%vregX:sub32<undef> =` to represent this.</div><div><br class=""></div><div>So today you are probably out of luck when coming from the MC side of things. I think adding a OperandFlag in MCInstrDesc would be a great idea and could be a first step towards retiring SUBREG_TO_REG.</div><div><br class=""></div><div>- Matthias</div><div><br class=""></div><blockquote type="cite" class=""><div class=""><div style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><div class=""><br class=""></div><div class="">Matthias?<br class=""><div class=""><br class=""></div><div class="">-Andy<br class=""><div class=""><br class=""></div><div class=""><blockquote type="cite" class="">1) Partial register updates versus full register updates.<br class=""><br class="">On x86-64, a 32-bit GPR write fully updates the super-register. Example:<br class=""> add %edi %eax ## eax += edi<br class=""><br class="">Here, register %eax aliases the lower half of 64-bit register %rax. On x86-64,<br class="">register %rax is fully updated by the 'add' (the upper half of %rax is zeroed).<br class="">Essentially, it "kills" any previous definition of (the upper half of) register<br class="">%rax.<br class=""><br class="">On the other hand, 8/16 bit register writes only perform a so-called "partial<br class="">register update". Example:<br class=""> add %di, %ax ## ax += di<br class=""><br class="">Here, register %eax is only partially updated. To be more specific, the lower<br class="">half of %eax is set, and the upper half is left unchanged. There is also no<br class="">change in the upper 48 bits of register %rax.<br class=""><br class="">To get accurate performance analysis, the tool has to know which instructions<br class="">perform a partial register update, and which instructions fully update the<br class="">destination's super-register.<br class=""><br class="">One way to expose this information is (again) via tablegen. For example, we<br class="">could add a flag in the tablegen instruction class to tag instructions that<br class="">perform partial register updates. Something like this: 'bit<br class="">hasPartialRegisterUpdate = 1'. However, this would force a `let<br class="">hasPartialRegisterUpdate = 0` on several instruction definitions.<br class=""><br class="">Another approach is to have a MCSubtargetInfo hook similar to this:<br class=""> virtual bool updatesSuperRegisters(unsigned short opcode) { return false; }<br class=""><br class="">Targets will be able to override this method if needed. Again, this is just an<br class="">idea. But the plan is to have this fixed as a future development.</blockquote></div></div></div></div></div></blockquote></div><br class=""></body></html>