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<p class="MsoNormal">Hi,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">What is the best way to model a scheduler for a VLIW in-order architecture?<o:p></o:p></p>
<p class="MsoNormal">I’ve looked at the Hexagon and R600 architectures and they are using itineraries. I wanted to understand the benefit in using itineraries over the per operand scheduling.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I also found this thread from almost 2 years ago:<o:p></o:p></p>
<p class="MsoNormal"><a href="http://lists.llvm.org/pipermail/llvm-dev/2016-April/098763.html">http://lists.llvm.org/pipermail/llvm-dev/2016-April/098763.html</a><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">At that time it seemed the itineraries are a better choice, but is it still the case?<o:p></o:p></p>
<p class="MsoNormal">Also, in this thread Phil says:<o:p></o:p></p>
<p class="MsoNormal">“Some of the constraints that can be found in in-order micro architectures cannot be expressed in the per-operand scheduling model”<o:p></o:p></p>
<p class="MsoNormal">Does anybody have an example of such constraints that will be harder to model with per operand scheduling?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Thanks,<o:p></o:p></p>
<p class="MsoNormal">Marina<o:p></o:p></p>
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