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</o:shapelayout></xml><![endif]--></head><body lang=EN-IE link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;color:#943634;mso-fareast-language:EN-US'>Hi Matthias,<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;color:#943634;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;color:#943634;mso-fareast-language:EN-US'>I suspect I am more worried than concerned, meaning that I accept that such calls “might be” possible, but I am also currently aware of none. But because I have no control (other than source editing) over the sequence of passes that occur between “pre-RA” scheduling and “post-RA” scheduling, I guess my concern is about being 100% sure about when RA happens.<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;color:#943634;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;color:#943634;mso-fareast-language:EN-US'>I have not observed any current passes (other than frame lowering) that can cause lowering to occur between the two scheduling passes. I am quite happy to handle this with a flag which at the end of my “pre-RA” pass, assumes that RA is run. Worst case, slightly less efficient code. If there was something in TII, my preference is simple: ‘</span><span style='font-family:"Courier New";color:black;mso-fareast-language:EN-US'>bool isPreRA() const</span><span style='font-family:"Book Antiqua",serif;color:#943634;mso-fareast-language:EN-US'>’ and ‘</span><span style='font-family:"Courier New";color:black;mso-fareast-language:EN-US'>bool isPostRA() const</span><span style='font-family:"Book Antiqua",serif;color:#943634;mso-fareast-language:EN-US'>’, or something along those lines; not sure it would be appropriate to TII though, perhaps “</span><span style='font-family:"Courier New";color:black;mso-fareast-language:EN-US'>MachineFunction</span><span style='font-family:"Book Antiqua",serif;color:#943634;mso-fareast-language:EN-US'>”? Or even in the pass manager interface?<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;color:#943634;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;color:#943634;mso-fareast-language:EN-US'>All the best,<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;color:#943634;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;color:#943634;mso-fareast-language:EN-US'> MartinO<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;color:#943634;mso-fareast-language:EN-US'><o:p> </o:p></span></p><div><div style='border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0cm 0cm 0cm'><p class=MsoNormal><b><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri",sans-serif'>From:</span></b><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri",sans-serif'> mbraun@apple.com [mailto:mbraun@apple.com] <br><b>Sent:</b> 17 January 2018 18:04<br><b>To:</b> Martin J. O'Riordan <MartinO@theheart.ie><br><b>Cc:</b> Craig Topper <craig.topper@gmail.com>; LLVM Developers <llvm-dev@lists.llvm.org><br><b>Subject:</b> Re: [llvm-dev] Checking when Register Allocation has been performed<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal><br><br><o:p></o:p></p><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><p class=MsoNormal>On Jan 16, 2018, at 11:31 PM, Martin J. O'Riordan <<a href="mailto:MartinO@theheart.ie">MartinO@theheart.ie</a>> wrote:<o:p></o:p></p></div><p class=MsoNormal><o:p> </o:p></p><div><div><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;color:#943634'>Thanks Matthias,</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;color:#943634'> </span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;color:#943634'>I have both a pre-RA and a post-RA scheduler, and I had thought that I could track “has RA happened?” by setting a flag in my pre-RA scheduler as it completes - my suspicion (which you have confirmed) was that “#vregs == 0” was not a safe assumption. What I cannot be sure of, is what passes execute after my pre-RA scheduler but before RA, and what passes execute after RA but before my post-RA scheduler since this is largely target-independent. If any of those passes trigger a custom lowering action (frame setup for example), and it requires additional scratch registers, then my code generation strategy needs to change. As it happens, I know that frame lowering always occurs post-RA so that is not a real example, but is it possible that another pass between pre-RA and post-RA scheduling could trigger lowering actions? If not, then setting a flag in my pre-RA scheduler will solve the problem perfectly.</span><o:p></o:p></p></div></div></blockquote><div><p class=MsoNormal>Do you have a specific callback in TargetInstrInfo or similar in mind? I would expect them to either be used pre-ra or post-ra but not both...<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>- Matthias<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div></div></div></body></html>