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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">>The standard argument against trying to introduce "scope-like" mechanisms to LLVM IR is inlining;<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">>unless you're going to prevent functions that use stricter/laxer FP rules from being inlined >into<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">>each other (which sounds disastrous), you're going to need to communicate strictness on an<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">>instruction-by-instruction basis. If the backend wants to handle that by using the strictest
<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">>rule that it sees in use anywhere in the function because pattern-matching is otherwise too<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">>error-prone, ok, that's its right; but the IR really should be per-instruction.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">I added a function level attribute, strictfp, which is meant to help with this. I don’t believe the inlining handling of the attribute is implemented yet, but
what I’m thinking is that we would never inline a function that had the strictfp attribute and if we inlined a non-strictfp function into a strictfp function, we would transform any FP operations into their constrained equivalents at that time. In the short
term, we’d probably just block both types of inlining.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">It may sound disastrous, but I think there’s an understanding that using strict FP semantics is going to significantly inhibit optimizations. In the short term,
that’s actually the purpose of the constrained intrinsics -- to disable all optimizations until we can teach the optimizer to do things correctly. The plan is that once this is all implemented to produce correct results, we’ll go back and try to re-enable
as many optimizations as possible, which may eventually include doing something more intelligent with inlining.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">With regard to your “instruction level” comments, my intention is that the use of the intrinsics will impose the necessary restrictions at the instruction level.
Optimizations (other than inlining) should never need to check the function level attribute. But if we mixed “raw” FP operations and constrained intrinsics within a single function there would be no way to prevent motion of the “raw” operations across the
intrinsics.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">The reason I brought up the scope level nature of the pragma was just to suggest that it might be a property that we could take advantage of to handle the transition
from IR to MIR. I haven’t come up with a way to bake the strict FP information into the instructions across the ISel boundary, but I think it might be possible to temporarily add it to a block and then have an early machine code pass that used this information
in some way once the MIR was all in place. I’m open to the possibility that that was a bad idea.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">-Andy<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><a name="_MailEndCompose"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></a></p>
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<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> rjmccall@apple.com [mailto:rjmccall@apple.com]
<br>
<b>Sent:</b> Tuesday, January 09, 2018 11:12 AM<br>
<b>To:</b> Kaylor, Andrew <andrew.kaylor@intel.com><br>
<b>Cc:</b> Ulrich Weigand <Ulrich.Weigand@de.ibm.com>; kpn@neutralgood.org; bumblebritches57@gmail.com; bob.huemmer@sas.com; llvm-dev <llvm-dev@lists.llvm.org>; Richard Smith <richard@metafoo.co.uk>; cfe-dev@lists.llvm.org<br>
<b>Subject:</b> Re: [cfe-dev] Why is #pragma STDC FENV_ACCESS not supported?<o:p></o:p></span></p>
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<p class="MsoNormal">On Jan 9, 2018, at 1:53 PM, Kaylor, Andrew via cfe-dev <<a href="mailto:cfe-dev@lists.llvm.org">cfe-dev@lists.llvm.org</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">I think we’re going to need to create a new mechanism to communicate strict FP modes to the backend. I think we need to avoid doing anything that will require
re-inventing or duplicating all of the pattern matching that goes on in instruction selection (which is the reason we’re currently dropping that information). I’m out of my depth on this transition, but I think maybe we could handle it with some kind of attribute
on the MBB.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">In C/C++, at least, it’s my understanding that the pragmas always apply at the scope-level (as opposed to having the possibility of being instruction-specific),
and we’ve previously agreed that our implementation will really need to apply the rules across entire functions in the sense that if any part of a function uses the constrained intrinsics all FP operations in the function will need to use them (though different
metadata arguments may be used in different scopes). So I think that opens our options a bit.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Regarding constant folding, I think you are correct that it isn’t happening anywhere in the backends at the moment. There is some constant folding done during
instruction selection, but the existing mechanism prevents that. My concern is that given LLVM’s development model, if there is nothing in place to prevent constant folding and no consensus that it shouldn’t be allowed then we should probably believe that
someone will eventually do it.</span><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">The standard argument against trying to introduce "scope-like" mechanisms to LLVM IR is inlining; unless you're going to prevent functions that use stricter/laxer FP rules from being inlined into each other (which sounds disastrous), you're
going to need to communicate strictness on an instruction-by-instruction basis. If the backend wants to handle that by using the strictest rule that it sees in use anywhere in the function because pattern-matching is otherwise too error-prone, ok, that's
its right; but the IR really should be per-instruction.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">John.<o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">-Andy</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"> </span><o:p></o:p></p>
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<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span class="apple-converted-space"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> </span></span><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">Ulrich
Weigand [<a href="mailto:Ulrich.Weigand@de.ibm.com"><span style="color:#954F72">mailto:Ulrich.Weigand@de.ibm.com</span></a>]<span class="apple-converted-space"> </span><br>
<b>Sent:</b><span class="apple-converted-space"> </span>Tuesday, January 09, 2018 9:59 AM<br>
<b>To:</b><span class="apple-converted-space"> </span>Kaylor, Andrew <<a href="mailto:andrew.kaylor@intel.com"><span style="color:#954F72">andrew.kaylor@intel.com</span></a>>;<span class="apple-converted-space"> </span><a href="mailto:kpn@neutralgood.org"><span style="color:#954F72">kpn@neutralgood.org</span></a><br>
<b>Cc:</b><span class="apple-converted-space"> </span>Hal Finkel <<a href="mailto:hfinkel@anl.gov"><span style="color:#954F72">hfinkel@anl.gov</span></a>>; Richard Smith <<a href="mailto:richard@metafoo.co.uk"><span style="color:#954F72">richard@metafoo.co.uk</span></a>>;<span class="apple-converted-space"> </span><a href="mailto:bob.huemmer@sas.com"><span style="color:#954F72">bob.huemmer@sas.com</span></a>;<span class="apple-converted-space"> </span><a href="mailto:bumblebritches57@gmail.com"><span style="color:#954F72">bumblebritches57@gmail.com</span></a>;<span class="apple-converted-space"> </span><a href="mailto:wei.ding2@amd.com"><span style="color:#954F72">wei.ding2@amd.com</span></a>;<span class="apple-converted-space"> </span><a href="mailto:cfe-dev@lists.llvm.org"><span style="color:#954F72">cfe-dev@lists.llvm.org</span></a>;
llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org"><span style="color:#954F72">llvm-dev@lists.llvm.org</span></a>><br>
<b>Subject:</b><span class="apple-converted-space"> </span>Re: [cfe-dev] Why is #pragma STDC FENV_ACCESS not supported?</span><o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:10.0pt">Andrew Kaylor wrote:</span><br>
<br>
<tt><span style="font-size:10.0pt">>In general, the current "strict FP" handling stops at instruction</span></tt><br>
<tt><span style="font-size:10.0pt">>selection. At the MachineIR level we don't currently have a mechanism</span></tt><br>
<tt><span style="font-size:10.0pt">>to prevent inappropriate optimizations based on floating point</span></tt><br>
<tt><span style="font-size:10.0pt">>constraints, or indeed to convey such constraints to the backend.</span></tt><br>
<tt><span style="font-size:10.0pt">>Implicit register use modeling may provide some restriction on some</span></tt><br>
<tt><span style="font-size:10.0pt">>architectures, but this is definitely lacking for X86 targets. On the</span></tt><br>
<tt><span style="font-size:10.0pt">>other hand, I'm not aware of any specific current problems, so in many</span></tt><br>
<tt><span style="font-size:10.0pt">>cases we may "get lucky" and have the correct thing happen by chance.</span></tt><br>
<tt><span style="font-size:10.0pt">>Obviously that's not a viable long term solution. I have a rough plan</span></tt><br>
<tt><span style="font-size:10.0pt">>for adding improved register modeling to the X86 backend, which should</span></tt><br>
<tt><span style="font-size:10.0pt">>take care of instruction scheduling issues, but we'd still need a</span></tt><br>
<tt><span style="font-size:10.0pt">>mechanism to prevent constant folding optimizations and such.</span></tt><br>
<span style="font-size:10.0pt"><br>
Given that Kevin intends to target SystemZ, I'll be happy to work on the SystemZ back-end support for this feature. I agree that we should be using implicit control register dependencies, which will at least prevent moving floating-point operations across instructions
that e.g. change rounding modes. However, the main property we need to model is that floating-point operations may *trap*. I guess this can be done using UnmodeledSideEffects, but I'm not quite clear on how to make this dependent on whether or not a "strict"
operation is requested (without duplicating all the instruction patterns ...).</span><br>
<br>
<span style="font-size:10.0pt">Once we do use something like UnmodeledSideEffects, I think MachineIR passes should handle everything correctly; in the end, the requirements are not really different from those of other trapping instructions. B.t.w. I don't think
anybody does constant folding on floating-point constants at the MachineIR level anyway ... have you seen this anywhere?</span><br>
<br>
<span style="font-size:10.0pt"><br>
Mit freundlichen Gruessen / Best Regards<br>
<br>
Ulrich Weigand<br>
<br>
--<span class="apple-converted-space"> </span><br>
Dr. Ulrich Weigand | Phone: +49-7031/16-3727<br>
STSM, GNU/Linux compilers and toolchain<br>
IBM Deutschland Research & Development GmbH<br>
Vorsitzende des Aufsichtsrats: Martina Koederitz | Geschäftsführung: Dirk Wittkopp<br>
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294</span><o:p></o:p></p>
<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica",sans-serif">_______________________________________________<br>
cfe-dev mailing list<br>
</span><a href="mailto:cfe-dev@lists.llvm.org"><span style="font-size:9.0pt;font-family:"Helvetica",sans-serif;color:#954F72">cfe-dev@lists.llvm.org</span></a><span style="font-size:9.0pt;font-family:"Helvetica",sans-serif"><br>
</span><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-dev"><span style="font-size:9.0pt;font-family:"Helvetica",sans-serif;color:#954F72">http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-dev</span></a><o:p></o:p></p>
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