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<div style="direction: ltr;font-family: Tahoma;color: #000000;font-size: 10pt;">Hi Sean,
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<div>I didn't implement that particular functionality as it was before my time at MIPS, Akira (+cc) may recall the</div>
<div>specifics why he took that approach. </div>
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<div>As far as I can see, the MIPS' approach pre-dates the AArch64 style approach which is also used by Lanai &</div>
<div>RISCV as Alex highlights, so I believe it was a novel approach. It appears no other targets take this approach</div>
<div>of a late SelectionDAG pass.</div>
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<div>Thanks,</div>
<div>Simon
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<div id="divRpF575918" style="direction: ltr;"><font face="Tahoma" size="2" color="#000000"><b>From:</b> Sean Silva [chisophugis@gmail.com]<br>
<b>Sent:</b> Sunday, December 24, 2017 4:43 AM<br>
<b>To:</b> Simon Dardis<br>
<b>Cc:</b> llvm-dev<br>
<b>Subject:</b> RE: [llvm-dev] Canonical way to handle zero registers?<br>
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<div dir="auto">Thanks, that sounds like it would work. Was this based on what any other target did? Or do any other targets take this approach?
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<div dir="auto">I just want to make sure that we don't already have a hook suitable for this. Overriding runOnFunction to run what could be described as just a "late SelectionDAG pass" sounds pretty intrusive. Do you remember other approaches that didn't work?</div>
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<div dir="auto">-- Sean Silva</div>
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<div class="gmail_quote">On Dec 22, 2017 2:17 PM, "Simon Dardis" <<a href="mailto:Simon.Dardis@mips.com" target="_blank">Simon.Dardis@mips.com</a>> wrote:<br type="attribution">
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<div style="direction:ltr; font-family:Tahoma; color:#000000; font-size:10pt">Hi Sean,
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<div>Have you looked at inheriting from llvm:SelectionDAGISel for your target, invoking runOnMachineFunction to perform</div>
<div>ISEL, then post processing <span style="font-size:10pt">the output by finding the cases where -1 is synthesized then used and replacing the uses</span></div>
<div><span style="font-size:10pt">of the synthesized -1 with the register wired to -1?</span></div>
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<div>The MIPS backend takes this approach for dealing with the zero register, see MipSEISelDAGToDAG.cpp for reference.</div>
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<div>Thanks,</div>
<div>Simon<br>
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<div id="m_4833981333199045773divRpF382613" style="direction:ltr"><font face="Tahoma" size="2" color="#000000"><b>From:</b> llvm-dev [<a href="mailto:llvm-dev-bounces@lists.llvm.org" target="_blank">llvm-dev-bounces@lists.llvm.<wbr>org</a>] on behalf of Sean
Silva via llvm-dev [<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>]<br>
<b>Sent:</b> Friday, December 22, 2017 5:22 AM<br>
<b>To:</b> llvm-dev<br>
<b>Subject:</b> [llvm-dev] Canonical way to handle zero registers?<br>
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<div dir="auto">I looked around the codebase and didn't see anything that obviously looked like the natural place to turn constant zero immediates into zero-registers (i.e. registers that always return zero when read). Right now we are expanding them in ISelLowering::LowerOperation
but that seems too early.
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<div dir="auto">The specific issue I'm hitting is that we have a register that reads as -1 and so when we replace -1 too early with this register, the standard "not" pattern (xor x, -1) will fail to match to "not".</div>
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<div dir="auto">Thanks,</div>
<div dir="auto">Sean Silva</div>
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