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<p class="MsoNormal">Can anyone suggest how to define an opcode that takes a pair of registers on a 32-bit architecture but a single 64-bit wide register on a 64-bit architecture? For example, the following instruction converts a double to a single. The source
operand is a register of class "Pair64". Is there a way to define it such that the register class is defined at runtime when we know if it should be a 64-bit register class?<o:p></o:p></p>
<p class="MsoNormal"><o:p></o:p></p>
<p class="MsoNormal">def FD2S_rr: RRX<0b00110,0,0,0, (outs Core32:$a), (ins Pair64:$b),<o:p></o:p></p>
<p class="MsoNormal"> "FD2S\t$a,$b"),[(set f32:$a, (fpround f64:$b))]>;<o:p></o:p></p>
<p class="MsoNormal"><o:p></o:p></p>
<p class="MsoNormal">Example register classes:<o:p></o:p></p>
<p class="MsoNormal"><o:p></o:p></p>
<p class="MsoNormal">def Core32: RegisterClass<"XYZ", [i32,f32], 32,<o:p></o:p></p>
<p class="MsoNormal"> (add R0,R1,R2,R3,...<o:p></o:p></p>
<p class="MsoNormal"><o:p></o:p></p>
<p class="MsoNormal">def Pair64: RegisterClass<"XYZ", [i64,f64], 64,...<o:p></o:p></p>
<p class="MsoNormal"> (add R0R1, R2R3,...<o:p></o:p></p>
<p class="MsoNormal"><o:p></o:p></p>
<p class="MsoNormal">def WideCore : RegisterClass<"XYZ", [i64,f64], 64,<o:p></o:p></p>
<p class="MsoNormal"> (add R0_64, R1_64 ...<o:p></o:p></p>
<p class="MsoNormal"><o:p></o:p></p>
<p class="MsoNormal"> <o:p></o:p></p>
<p class="MsoNormal">def R0 : Core<0, "%r0">, DwarfRegNum<[0]>;<o:p></o:p></p>
<p class="MsoNormal">def R1 : Core<1, "%r1">, DwarfRegNum<[1]>;<o:p></o:p></p>
<p class="MsoNormal">def R2 : Core<2, "%r2">, DwarfRegNum<[2]>;<o:p></o:p></p>
<p class="MsoNormal">def R3 : Core<3, "%r3">, DwarfRegNum<[3]>;<o:p></o:p></p>
<p class="MsoNormal"><o:p></o:p></p>
<p class="MsoNormal">def R0R1 : CorePair<0,"%r0",[R0,R1] >;<o:p></o:p></p>
<p class="MsoNormal">def R2R3 : CorePair<2,"%r2",[R2,R3] >;<o:p></o:p></p>
<p class="MsoNormal"><o:p></o:p></p>
<p class="MsoNormal">def R0_64 : Core64<0, "%r0", [R0]>, DwarfRegNum<[0]>;<o:p></o:p></p>
<p class="MsoNormal">def R1_64 : Core64<1, "%r1", [R1]>, DwarfRegNum<[1]>;<o:p></o:p></p>
<p class="MsoNormal"><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">As I understand it, tablegen emits static tables with hard references to register classes and such. I fear that I’ll need to duplicate all the opcodes that have Pair64 operands and define identical ones with WideCore operands. I can imagine
changing the tablegen backend to emit tables with dynamic initializers.<o:p></o:p></p>
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