********** GREEDY REGISTER ALLOCATION ********** ********** Function: yuv2rgb_mod ********** Compute Spill Weights ********** ********** Function: yuv2rgb_mod ********** INTERVALS ********** ZERO EMPTY R5 [0B,72r:0) 0@0B-phi R6 [0B,32r:0) 0@0B-phi R7 [0B,16r:0) 0@0B-phi V0 EMPTY %vreg0 [432r,448r:0) 0@432r %vreg1 [240r,1824r:0) 0@240r %vreg2 [528r,1792B:0) 0@528r %vreg3 [544r,1792B:0) 0@544r %vreg12 [1920r,2864B:0) 0@1920r %vreg13 [1976r,2864B:0) 0@1976r %vreg14 [1984r,2864B:0) 0@1984r %vreg23 [16r,1968r:0) 0@16r %vreg24 [64r,80r:0) 0@64r %vreg26 [144r,176r:0) 0@144r %vreg28 [224r,240r:0) 0@224r %vreg29 [256r,288r:0) 0@256r %vreg31 [336r,352r:0) 0@336r %vreg32 [352r,368r:0) 0@352r %vreg33 [368r,384r:0) 0@368r %vreg34 [448r,480r:0) 0@448r %vreg35 [948r,1320r:0) 0@948r %vreg36 [872r,948r:0) 0@872r %vreg37 [864r,880r:0) 0@864r %vreg38 [952r,1048r:0) 0@952r %vreg39 [880r,952r:0) 0@880r %vreg40 [560r,1792B:0) 0@560r %vreg41 [968r,1096r:0) 0@968r %vreg42 [1048r,1248r:0) 0@1048r %vreg43 [944r,960r:0) 0@944r %vreg44 [976r,1096r:0) 0@976r %vreg45 [960r,976r:0) 0@960r %vreg46 [1096r,1184r:0) 0@1096r %vreg47 [576r,1792B:0) 0@576r %vreg48 [1008r,1128r:0) 0@1008r %vreg49 [1128r,1240r:0) 0@1128r %vreg50 [592r,1792B:0) 0@592r %vreg51 [1040r,1256r:0) 0@1040r %vreg52 [1240r,1272r:0) 0@1240r %vreg53 [1272r,1400r:0) 0@1272r %vreg54 [608r,1792B:0) 0@608r %vreg55 [1088r,1176r:0) 0@1088r %vreg56 [1176r,1192r:0) 0@1176r %vreg57 [624r,1792B:0) 0@624r %vreg58 [1120r,1192r:0) 0@1120r %vreg59 [1192r,1288r:0) 0@1192r %vreg60 [1288r,1316r:0) 0@1288r %vreg61 [640r,1792B:0) 0@640r %vreg62 [1168r,1184r:0) 0@1168r %vreg63 [1184r,1256r:0) 0@1184r %vreg64 [1256r,1316r:0) 0@1256r %vreg65 [1316r,1604r:0) 0@1316r %vreg66 [656r,1792B:0) 0@656r %vreg67 [1232r,1248r:0) 0@1232r %vreg68 [1248r,1280r:0) 0@1248r %vreg69 [672r,1792B:0) 0@672r %vreg70 [1264r,1280r:0) 0@1264r %vreg71 [1280r,1320r:0) 0@1280r %vreg72 [1320r,1672r:0) 0@1320r %vreg73 [724r,1792B:0) 0@724r %vreg74 [1312r,1672r:0) 0@1312r %vreg75 [1328r,1400r:0) 0@1328r %vreg76 [1400r,1512r:0) 0@1400r %vreg77 [728r,1792B:0) 0@728r %vreg78 [1360r,1512r:0) 0@1360r %vreg79 [1512r,1544r:0) 0@1512r %vreg80 [1392r,1544r:0) 0@1392r %vreg81 [1492r,1604r:0) 0@1492r %vreg82 [1604r,1624r:0) 0@1604r %vreg83 [1496r,1624r:0) 0@1496r %vreg84 [1624r,1656r:0) 0@1624r %vreg85 [1488r,1504r:0) 0@1488r %vreg86 [1504r,1656r:0) 0@1504r %vreg87 [1536r,1672r:0) 0@1536r %vreg88 [1672r,1704r:0) 0@1672r %vreg89 [1608r,1704r:0) 0@1608r %vreg90 [1704r,1720r:0) 0@1704r %vreg91 [1600r,1616r:0) 0@1600r %vreg92 [1616r,1720r:0) 0@1616r %vreg93 [1696r,1760r:0) 0@1696r %vreg94 [1808r,1840r:0) 0@1808r %vreg95 [1936r,1976r:0) 0@1936r %vreg96 [1968r,1984r:0) 0@1968r %vreg97 [2112r,2196r:0) 0@2112r %vreg98 [2196r,2568r:0) 0@2196r %vreg99 [2144r,2200r:0) 0@2144r %vreg100 [2200r,2216r:0) 0@2200r %vreg101 [2216r,2384r:0) 0@2216r %vreg102 [2192r,2208r:0) 0@2192r %vreg103 [2208r,2224r:0) 0@2208r %vreg104 [2224r,2336r:0) 0@2224r %vreg105 [2240r,2296r:0) 0@2240r %vreg106 [2296r,2344r:0) 0@2296r %vreg107 [2344r,2464r:0) 0@2344r %vreg108 [2288r,2304r:0) 0@2288r %vreg109 [2304r,2360r:0) 0@2304r %vreg110 [2360r,2392r:0) 0@2360r %vreg111 [2336r,2352r:0) 0@2336r %vreg112 [2352r,2392r:0) 0@2352r %vreg113 [2392r,2560r:0) 0@2392r %vreg114 [2384r,2400r:0) 0@2384r %vreg115 [2400r,2568r:0) 0@2400r %vreg116 [2568r,2696r:0) 0@2568r %vreg117 [2432r,2448r:0) 0@2432r %vreg118 [2448r,2504r:0) 0@2448r %vreg119 [2464r,2504r:0) 0@2464r %vreg120 [2504r,2536r:0) 0@2504r %vreg121 [2496r,2536r:0) 0@2496r %vreg122 [2528r,2544r:0) 0@2528r %vreg123 [2544r,2576r:0) 0@2544r %vreg124 [2560r,2576r:0) 0@2560r %vreg125 [2576r,2632r:0) 0@2576r %vreg126 [2592r,2632r:0) 0@2592r %vreg127 [2624r,2640r:0) 0@2624r %vreg128 [2640r,2728r:0) 0@2640r %vreg129 [2696r,2728r:0) 0@2696r %vreg130 [2728r,2776r:0) 0@2728r %vreg131 [2688r,2776r:0) 0@2688r %vreg132 [2768r,2832r:0) 0@2768r %vreg133 [720r,768B:0)[768B,1712r:1)[1712r,1792B:2) 0@720r 1@768B-phi 2@1712r %vreg134 [736r,768B:0)[768B,1664r:1)[1664r,1792B:2) 0@736r 1@768B-phi 2@1664r %vreg135 [752r,768B:0)[768B,1648r:1)[1648r,1792B:2) 0@752r 1@768B-phi 2@1648r %vreg136 [152r,512B:0)[1824r,1872B:1)[1872B,1920r:2) 0@152r 1@1824r 2@1872B-phi %vreg137 [32r,2048B:0)[2048B,2772r:1)[2772r,2864B:2) 0@32r 1@2048B-phi 2@2772r %vreg138 [72r,2048B:0)[2048B,2736r:1)[2736r,2864B:2) 0@72r 1@2048B-phi 2@2736r %vreg139 [1904r,2048B:0)[2048B,2720r:1)[2720r,2864B:2) 0@1904r 1@2048B-phi 2@2720r RegMasks: ********** MACHINEINSTRS ********** # Machine code for function yuv2rgb_mod: NoPHIs, TracksLiveness Function Live Ins: %R5 in %vreg21, %R6 in %vreg22, %R7 in %vreg23 0B BB#0: derived from LLVM BB %entry Live Ins: %R5 %R6 %R7 16B %vreg23 = COPY %R7; GRegs:%vreg23 32B %vreg137 = COPY %R6; GRegs:%vreg137 64B %vreg24 = SFLTSri %vreg23, 1; FlagRegs:%vreg24 GRegs:%vreg23 72B %vreg138 = COPY %R5; GRegs:%vreg138 80B BF %vreg24, ; FlagRegs:%vreg24 96B J Successors according to CFG: BB#1(0x50000000 / 0x80000000 = 62.50%) BB#10(0x30000000 / 0x80000000 = 37.50%) 112B BB#1: derived from LLVM BB %for.body.preheader Predecessors according to CFG: BB#0 144B %vreg26 = SFLTUri %vreg23, 8; FlagRegs:%vreg26 GRegs:%vreg23 152B %vreg136 = ORri %ZERO, 0; GRegs:%vreg136 176B BF %vreg26, ; FlagRegs:%vreg26 192B J Successors according to CFG: BB#8(0x40000000 / 0x80000000 = 50.00%) BB#2(0x40000000 / 0x80000000 = 50.00%) 208B BB#2: derived from LLVM BB %min.iters.checked Predecessors according to CFG: BB#1 224B %vreg28 = ADDri %ZERO, -8; GRegs:%vreg28 240B %vreg1 = ANDrr %vreg23, %vreg28; GRegs:%vreg1,%vreg23,%vreg28 256B %vreg29 = SFEQri %vreg1, 0; FlagRegs:%vreg29 GRegs:%vreg1 288B BF %vreg29, ; FlagRegs:%vreg29 304B J Successors according to CFG: BB#8(0x30000000 / 0x80000000 = 37.50%) BB#3(0x50000000 / 0x80000000 = 62.50%) 320B BB#3: derived from LLVM BB %vector.memcheck Predecessors according to CFG: BB#2 336B %vreg31 = MULri %vreg23, 12; GRegs:%vreg31,%vreg23 352B %vreg32 = ADDrr %vreg138, %vreg31; GRegs:%vreg32,%vreg138,%vreg31 368B %vreg33 = SFLEUrr %vreg32, %vreg138; FlagRegs:%vreg33 GRegs:%vreg32,%vreg138 384B BF %vreg33, ; FlagRegs:%vreg33 400B J Successors according to CFG: BB#4(0x60000000 / 0x80000000 = 75.00%) BB#5(0x20000000 / 0x80000000 = 25.00%) 416B BB#4: derived from LLVM BB %vector.memcheck Predecessors according to CFG: BB#3 432B %vreg0 = SLLri %vreg23, 1; GRegs:%vreg0,%vreg23 448B %vreg34 = SFLTSrr %vreg0, %vreg23; FlagRegs:%vreg34 GRegs:%vreg0,%vreg23 480B BF %vreg34, ; FlagRegs:%vreg34 496B J Successors according to CFG: BB#8(0x55555555 / 0x80000000 = 66.67%) BB#5(0x2aaaaaab / 0x80000000 = 33.33%) 512B BB#5: derived from LLVM BB %vector.body.preheader Predecessors according to CFG: BB#3 BB#4 528B %vreg2 = SLLri %vreg23, 3; GRegs:%vreg2,%vreg23 544B %vreg3 = SLLri %vreg23, 2; GRegs:%vreg3,%vreg23 560B %vreg40 = VADDvi %V0, ; VRegs:%vreg40 576B %vreg47 = VADDvi %V0, ; VRegs:%vreg47 592B %vreg50 = VADDvi %V0, ; VRegs:%vreg50 608B %vreg54 = VADDvi %V0, ; VRegs:%vreg54 624B %vreg57 = VADDvi %V0, ; VRegs:%vreg57 640B %vreg61 = VADDvi %V0, ; VRegs:%vreg61 656B %vreg66 = VADDvi %V0, ; VRegs:%vreg66 672B %vreg69 = VADDvi %V0, ; VRegs:%vreg69 720B %vreg133 = COPY %vreg137; GRegs:%vreg133,%vreg137 724B %vreg73 = VADDvi %V0, ; VRegs:%vreg73 728B %vreg77 = VADDvi %V0, 0; VRegs:%vreg77 736B %vreg134 = COPY %vreg138; GRegs:%vreg134,%vreg138 752B %vreg135 = COPY %vreg1; GRegs:%vreg135,%vreg1 Successors according to CFG: BB#6(?%) 768B BB#6: derived from LLVM BB %vector.body Predecessors according to CFG: BB#5 BB#6 864B %vreg37 = ADDrr %vreg3, %vreg133; GRegs:%vreg37,%vreg3,%vreg133 872B %vreg36 = COPY %vreg133; VRegs:%vreg36 GRegs:%vreg133 880B %vreg39 = COPY %vreg37; VRegs:%vreg39 GRegs:%vreg37 944B %vreg43 = ADDrr %vreg2, %vreg133; GRegs:%vreg43,%vreg2,%vreg133 948B %vreg35 = VLW %vreg36, 0; VRegs:%vreg35,%vreg36 952B %vreg38 = VLW %vreg39, 0; VRegs:%vreg38,%vreg39 960B %vreg45 = COPY %vreg43; VRegs:%vreg45 GRegs:%vreg43 968B %vreg41 = VLW %vreg40, 0; VRegs:%vreg41,%vreg40 976B %vreg44 = VLW %vreg45, 0; VRegs:%vreg44,%vreg45 1008B %vreg48 = VLW %vreg47, 0; VRegs:%vreg48,%vreg47 1040B %vreg51 = VLW %vreg50, 0; VRegs:%vreg51,%vreg50 1048B %vreg42 = VADDvv %vreg38, %vreg41; VRegs:%vreg42,%vreg38,%vreg41 1088B %vreg55 = VLW %vreg54, 0; VRegs:%vreg55,%vreg54 1096B %vreg46 = VADDvv %vreg44, %vreg41; VRegs:%vreg46,%vreg44,%vreg41 1120B %vreg58 = VLW %vreg57, 0; VRegs:%vreg58,%vreg57 1128B %vreg49 = VMULvv %vreg46, %vreg48; VRegs:%vreg49,%vreg46,%vreg48 1168B %vreg62 = VLW %vreg61, 0; VRegs:%vreg62,%vreg61 1176B %vreg56 = VMULvv %vreg42, %vreg55; VRegs:%vreg56,%vreg42,%vreg55 1184B %vreg63 = VMULvv %vreg46, %vreg62; VRegs:%vreg63,%vreg46,%vreg62 1192B %vreg59 = VSRAvv %vreg56, %vreg58; VRegs:%vreg59,%vreg56,%vreg58 1232B %vreg67 = VLW %vreg66, 0; VRegs:%vreg67,%vreg66 1240B %vreg52 = VSRAvv %vreg49, %vreg51; VRegs:%vreg52,%vreg49,%vreg51 1248B %vreg68 = VMULvv %vreg42, %vreg67; VRegs:%vreg68,%vreg42,%vreg67 1256B %vreg64 = VSRAvv %vreg63, %vreg51; VRegs:%vreg64,%vreg63,%vreg51 1264B %vreg70 = VLW %vreg69, 0; VRegs:%vreg70,%vreg69 1272B %vreg53 = VADDvv %vreg52, %vreg35; VRegs:%vreg53,%vreg52,%vreg35 1280B %vreg71 = VSRAvv %vreg68, %vreg70; VRegs:%vreg71,%vreg68,%vreg70 1288B %vreg60 = VSUB %vreg35, %vreg59; VRegs:%vreg60,%vreg35,%vreg59 1312B %vreg74 = VLW %vreg73, 0; VRegs:%vreg74,%vreg73 1316B %vreg65 = VSUB %vreg60, %vreg64; VRegs:%vreg65,%vreg60,%vreg64 1320B %vreg72 = VADDvv %vreg71, %vreg35; VRegs:%vreg72,%vreg71,%vreg35 1328B %vreg75 = VSFLTSP0vv %vreg53, %vreg74; VP0Regs:%vreg75 VRegs:%vreg53,%vreg74 1360B %vreg78 = VSFGTSP0vv %vreg53, %vreg77; VP0Regs:%vreg78 VRegs:%vreg53,%vreg77 1392B %vreg80 = COPY %vreg134; VRegs:%vreg80 GRegs:%vreg134 1400B %vreg76 = VCMOVvv %vreg75, %vreg53, %vreg74; VRegs:%vreg76,%vreg53,%vreg74 VP0Regs:%vreg75 1488B %vreg85 = ADDrr %vreg3, %vreg134; GRegs:%vreg85,%vreg3,%vreg134 1492B %vreg81 = VSFLTSP0vv %vreg65, %vreg74; VP0Regs:%vreg81 VRegs:%vreg65,%vreg74 1496B %vreg83 = VSFGTSP0vv %vreg65, %vreg77; VP0Regs:%vreg83 VRegs:%vreg65,%vreg77 1504B %vreg86 = COPY %vreg85; VRegs:%vreg86 GRegs:%vreg85 1512B %vreg79 = VCMOVvv %vreg78, %vreg76, %vreg77; VRegs:%vreg79,%vreg76,%vreg77 VP0Regs:%vreg78 1536B %vreg87 = VSFLTSP0vv %vreg72, %vreg74; VP0Regs:%vreg87 VRegs:%vreg72,%vreg74 1544B VSW %vreg79, %vreg80, 0; VRegs:%vreg79,%vreg80 1600B %vreg91 = ADDrr %vreg2, %vreg134; GRegs:%vreg91,%vreg2,%vreg134 1604B %vreg82 = VCMOVvv %vreg81, %vreg65, %vreg74; VRegs:%vreg82,%vreg65,%vreg74 VP0Regs:%vreg81 1608B %vreg89 = VSFGTSP0vv %vreg72, %vreg77; VP0Regs:%vreg89 VRegs:%vreg72,%vreg77 1616B %vreg92 = COPY %vreg91; VRegs:%vreg92 GRegs:%vreg91 1624B %vreg84 = VCMOVvv %vreg83, %vreg82, %vreg77; VRegs:%vreg84,%vreg82,%vreg77 VP0Regs:%vreg83 1648B %vreg135 = ADDri %vreg135, -8; GRegs:%vreg135 1656B VSW %vreg84, %vreg86, 0; VRegs:%vreg84,%vreg86 1664B %vreg134 = ADDri %vreg134, 32; GRegs:%vreg134 1672B %vreg88 = VCMOVvv %vreg87, %vreg72, %vreg74; VRegs:%vreg88,%vreg72,%vreg74 VP0Regs:%vreg87 1696B %vreg93 = SFNEri %vreg135, 0; FlagRegs:%vreg93 GRegs:%vreg135 1704B %vreg90 = VCMOVvv %vreg89, %vreg88, %vreg77; VRegs:%vreg90,%vreg88,%vreg77 VP0Regs:%vreg89 1712B %vreg133 = ADDri %vreg133, 32; GRegs:%vreg133 1720B VSW %vreg90, %vreg92, 0; VRegs:%vreg90,%vreg92 1760B BF %vreg93, ; FlagRegs:%vreg93 1776B J Successors according to CFG: BB#7(0x04000000 / 0x80000000 = 3.12%) BB#6(0x7c000000 / 0x80000000 = 96.88%) 1792B BB#7: derived from LLVM BB %middle.block Predecessors according to CFG: BB#6 1808B %vreg94 = SFEQrr %vreg1, %vreg23; FlagRegs:%vreg94 GRegs:%vreg1,%vreg23 1824B %vreg136 = COPY %vreg1; GRegs:%vreg136,%vreg1 1840B BF %vreg94, ; FlagRegs:%vreg94 1856B J Successors according to CFG: BB#10(0x40000000 / 0x80000000 = 50.00%) BB#8(0x40000000 / 0x80000000 = 50.00%) 1872B BB#8: derived from LLVM BB %for.body.preheader103 Predecessors according to CFG: BB#1 BB#2 BB#4 BB#7 1904B %vreg139 = SUB %vreg23, %vreg136; GRegs:%vreg139,%vreg23,%vreg136 1920B %vreg12 = SLLri %vreg136, 2; GRegs:%vreg12,%vreg136 1936B %vreg95 = SLLri %vreg23, 3; GRegs:%vreg95,%vreg23 1968B %vreg96 = SLLri %vreg23, 2; GRegs:%vreg96,%vreg23 1976B %vreg13 = ADDrr %vreg12, %vreg95; GRegs:%vreg13,%vreg12,%vreg95 1984B %vreg14 = ADDrr %vreg12, %vreg96; GRegs:%vreg14,%vreg12,%vreg96 Successors according to CFG: BB#9(?%) 2048B BB#9: derived from LLVM BB %for.body Predecessors according to CFG: BB#8 BB#9 2112B %vreg97 = ADDrr %vreg12, %vreg137; GRegs:%vreg97,%vreg12,%vreg137 2144B %vreg99 = ADDrr %vreg14, %vreg137; GRegs:%vreg99,%vreg14,%vreg137 2192B %vreg102 = ADDrr %vreg13, %vreg137; GRegs:%vreg102,%vreg13,%vreg137 2196B %vreg98 = LW %vreg97, 0; mem:LD4[%sunkaddr49](tbaa=!2) GRegs:%vreg98,%vreg97 2200B %vreg100 = LW %vreg99, 0; mem:LD4[%uglygep1415](tbaa=!2) GRegs:%vreg100,%vreg99 2208B %vreg103 = LW %vreg102, 0; mem:LD4[%uglygep1213](tbaa=!2) GRegs:%vreg103,%vreg102 2216B %vreg101 = ADDri %vreg100, -128; GRegs:%vreg101,%vreg100 2224B %vreg104 = ADDri %vreg103, -128; GRegs:%vreg104,%vreg103 2240B %vreg105 = MULri %vreg104, 359; GRegs:%vreg105,%vreg104 2288B %vreg108 = MULri %vreg101, 11; GRegs:%vreg108,%vreg101 2296B %vreg106 = SRAri %vreg105, 8; GRegs:%vreg106,%vreg105 2304B %vreg109 = SRAri %vreg108, 5; GRegs:%vreg109,%vreg108 2336B %vreg111 = MULri %vreg104, 183; GRegs:%vreg111,%vreg104 2344B %vreg107 = ADDrr %vreg106, %vreg98; GRegs:%vreg107,%vreg106,%vreg98 2352B %vreg112 = SRAri %vreg111, 8; GRegs:%vreg112,%vreg111 2360B %vreg110 = SUB %vreg98, %vreg109; GRegs:%vreg110,%vreg98,%vreg109 2384B %vreg114 = MULri %vreg101, 227; GRegs:%vreg114,%vreg101 2392B %vreg113 = SUB %vreg110, %vreg112; GRegs:%vreg113,%vreg110,%vreg112 2400B %vreg115 = SRAri %vreg114, 7; GRegs:%vreg115,%vreg114 2432B %vreg117 = SFLTSri %vreg107, 255; FlagRegs:%vreg117 GRegs:%vreg107 2448B %vreg118 = CMOVri %vreg117, %vreg107, 255; GRegs:%vreg118,%vreg107 FlagRegs:%vreg117 2464B %vreg119 = SFGTSri %vreg107, 0; FlagRegs:%vreg119 GRegs:%vreg107 2496B %vreg121 = ADDrr %vreg12, %vreg138; GRegs:%vreg121,%vreg12,%vreg138 2504B %vreg120 = CMOVri %vreg119, %vreg118, 0; GRegs:%vreg120,%vreg118 FlagRegs:%vreg119 2528B %vreg122 = SFLTSri %vreg113, 255; FlagRegs:%vreg122 GRegs:%vreg113 2536B SW %vreg120, %vreg121, 0; mem:ST4[%sunkaddr52](tbaa=!2) GRegs:%vreg120,%vreg121 2544B %vreg123 = CMOVri %vreg122, %vreg113, 255; GRegs:%vreg123,%vreg113 FlagRegs:%vreg122 2560B %vreg124 = SFGTSri %vreg113, 0; FlagRegs:%vreg124 GRegs:%vreg113 2568B %vreg116 = ADDrr %vreg115, %vreg98; GRegs:%vreg116,%vreg115,%vreg98 2576B %vreg125 = CMOVri %vreg124, %vreg123, 0; GRegs:%vreg125,%vreg123 FlagRegs:%vreg124 2592B %vreg126 = ADDrr %vreg14, %vreg138; GRegs:%vreg126,%vreg14,%vreg138 2624B %vreg127 = SFLTSri %vreg116, 255; FlagRegs:%vreg127 GRegs:%vreg116 2632B SW %vreg125, %vreg126, 0; mem:ST4[%uglygep56](tbaa=!2) GRegs:%vreg125,%vreg126 2640B %vreg128 = CMOVri %vreg127, %vreg116, 255; GRegs:%vreg128,%vreg116 FlagRegs:%vreg127 2688B %vreg131 = ADDrr %vreg13, %vreg138; GRegs:%vreg131,%vreg13,%vreg138 2696B %vreg129 = SFGTSri %vreg116, 0; FlagRegs:%vreg129 GRegs:%vreg116 2720B %vreg139 = ADDri %vreg139, -1; GRegs:%vreg139 2728B %vreg130 = CMOVri %vreg129, %vreg128, 0; GRegs:%vreg130,%vreg128 FlagRegs:%vreg129 2736B %vreg138 = ADDri %vreg138, 4; GRegs:%vreg138 2768B %vreg132 = SFNEri %vreg139, 0; FlagRegs:%vreg132 GRegs:%vreg139 2772B %vreg137 = ADDri %vreg137, 4; GRegs:%vreg137 2776B SW %vreg130, %vreg131, 0; mem:ST4[%uglygep4](tbaa=!2) GRegs:%vreg130,%vreg131 2832B BF %vreg132, ; FlagRegs:%vreg132 2848B J Successors according to CFG: BB#10(0x04000000 / 0x80000000 = 3.12%) BB#9(0x7c000000 / 0x80000000 = 96.88%) 2864B BB#10: derived from LLVM BB %for.end Predecessors according to CFG: BB#0 BB#7 BB#9 2880B RetLR # End machine code for function yuv2rgb_mod. selectOrSplit GRegs:%vreg137 [32r,2048B:0)[2048B,2772r:1)[2772r,2864B:2) 0@32r 1@2048B-phi 2@2772r w=5.280274e-02 hints: %R6 assigning %vreg137 to %R6: R6 [32r,2048B:0)[2048B,2772r:1)[2772r,2864B:2) 0@32r 1@2048B-phi 2@2772r selectOrSplit GRegs:%vreg138 [72r,2048B:0)[2048B,2736r:1)[2736r,2864B:2) 0@72r 1@2048B-phi 2@2736r w=5.358210e-02 hints: %R5 assigning %vreg138 to %R5: R5 [72r,2048B:0)[2048B,2736r:1)[2736r,2864B:2) 0@72r 1@2048B-phi 2@2736r selectOrSplit GRegs:%vreg23 [16r,1968r:0) 0@16r w=2.316757e-03 hints: %R7 assigning %vreg23 to %R7: R7 [16r,1968r:0) 0@16r selectOrSplit GRegs:%vreg1 [240r,1824r:0) 0@240r w=4.462241e-04 assigning %vreg1 to %R3: R3 [240r,1824r:0) 0@240r selectOrSplit GRegs:%vreg2 [528r,1792B:0) 0@528r w=3.840383e-03 assigning %vreg2 to %R4: R4 [528r,1792B:0) 0@528r selectOrSplit GRegs:%vreg3 [544r,1792B:0) 0@544r w=3.877713e-03 assigning %vreg3 to %R8: R8 [544r,1792B:0) 0@544r selectOrSplit VRegs:%vreg40 [560r,1792B:0) 0@560r w=1.984397e-03 AllocationOrder(VRegs) = [ %V2 %V3 %V4 %V5 %V6 %V7 %V8 %V9 %V10 %V12 %V13 %V14 %V15 %V16 %V17 %V18 %V19 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 ] assigning %vreg40 to %V2: V2 [560r,1792B:0) 0@560r selectOrSplit VRegs:%vreg47 [576r,1792B:0) 0@576r w=2.004069e-03 assigning %vreg47 to %V3: V3 [576r,1792B:0) 0@576r selectOrSplit VRegs:%vreg50 [592r,1792B:0) 0@592r w=2.024135e-03 assigning %vreg50 to %V4: V4 [592r,1792B:0) 0@592r selectOrSplit VRegs:%vreg54 [608r,1792B:0) 0@608r w=2.044607e-03 assigning %vreg54 to %V5: V5 [608r,1792B:0) 0@608r selectOrSplit VRegs:%vreg57 [624r,1792B:0) 0@624r w=2.065497e-03 assigning %vreg57 to %V6: V6 [624r,1792B:0) 0@624r selectOrSplit VRegs:%vreg61 [640r,1792B:0) 0@640r w=2.086818e-03 assigning %vreg61 to %V7: V7 [640r,1792B:0) 0@640r selectOrSplit VRegs:%vreg66 [656r,1792B:0) 0@656r w=2.108584e-03 assigning %vreg66 to %V8: V8 [656r,1792B:0) 0@656r selectOrSplit VRegs:%vreg69 [672r,1792B:0) 0@672r w=2.130809e-03 assigning %vreg69 to %V9: V9 [672r,1792B:0) 0@672r selectOrSplit GRegs:%vreg133 [720r,768B:0)[768B,1712r:1)[1712r,1792B:2) 0@720r 1@768B-phi 2@1712r w=1.952650e-02 assigning %vreg133 to %R1: R1 [720r,768B:0)[768B,1712r:1)[1712r,1792B:2) 0@720r 1@768B-phi 2@1712r selectOrSplit VRegs:%vreg73 [724r,1792B:0) 0@724r w=2.206390e-03 assigning %vreg73 to %V10: V10 [724r,1792B:0) 0@724r selectOrSplit VRegs:%vreg77 [728r,1792B:0) 0@728r w=1.297901e-02 assigning %vreg77 to %V12: V12 [728r,1792B:0) 0@728r selectOrSplit GRegs:%vreg134 [736r,768B:0)[768B,1664r:1)[1664r,1792B:2) 0@736r 1@768B-phi 2@1664r w=1.974137e-02 assigning %vreg134 to %R2: R2 [736r,768B:0)[768B,1664r:1)[1664r,1792B:2) 0@736r 1@768B-phi 2@1664r selectOrSplit GRegs:%vreg135 [752r,768B:0)[768B,1648r:1)[1648r,1792B:2) 0@752r 1@768B-phi 2@1648r w=1.553873e-02 hints: %R3 assigning %vreg135 to %R13: R13 [752r,768B:0)[768B,1648r:1)[1648r,1792B:2) 0@752r 1@768B-phi 2@1648r selectOrSplit GRegs:%vreg139 [1904r,2048B:0)[2048B,2720r:1)[2720r,2864B:2) 0@1904r 1@2048B-phi 2@2720r w=9.651993e-02 assigning %vreg139 to %R3: R3 [1904r,2048B:0)[2048B,2720r:1)[2720r,2864B:2) 0@1904r 1@2048B-phi 2@2720r selectOrSplit GRegs:%vreg12 [1920r,2864B:0) 0@1920r w=2.907950e-02 assigning %vreg12 to %R4: R4 [1920r,2864B:0) 0@1920r selectOrSplit GRegs:%vreg13 [1976r,2864B:0) 0@1976r w=2.944339e-02 assigning %vreg13 to %R7: R7 [1976r,2864B:0) 0@1976r selectOrSplit GRegs:%vreg14 [1984r,2864B:0) 0@1984r w=2.962770e-02 assigning %vreg14 to %R8: R8 [1984r,2864B:0) 0@1984r selectOrSplit GRegs:%vreg136 [152r,512B:0)[1824r,1872B:1)[1872B,1920r:2) 0@152r 1@1824r 2@1872B-phi w=2.219331e-03 hints: %R3 assigning %vreg136 to %R4: R4 [152r,512B:0)[1824r,1872B:1)[1872B,1920r:2) 0@152r 1@1824r 2@1872B-phi selectOrSplit VP0Regs:%vreg78 [1360r,1512r:0) 0@1360r w=1.140633e-02 AllocationOrder(VP0Regs) = [ %VFLAG_P0 ] assigning %vreg78 to %VFLAG_P0: VFLAG_P0 [1360r,1512r:0) 0@1360r selectOrSplit VP0Regs:%vreg87 [1536r,1672r:0) 0@1536r w=1.174682e-02 assigning %vreg87 to %VFLAG_P0: VFLAG_P0 [1536r,1672r:0) 0@1536r selectOrSplit VP0Regs:%vreg83 [1496r,1624r:0) 0@1496r w=1.192480e-02 RS_Assign Cascade 0 should evict: %vreg87 [1536r,1672r:0) 0@1536r w= 1.174682e-02 should evict: %vreg78 [1360r,1512r:0) 0@1360r w= 1.140633e-02 evicting %VFLAG_P0 interference: Cascade 1 unassigning %vreg78 from %VFLAG_P0: VFLAG_P0 unassigning %vreg87 from %VFLAG_P0: VFLAG_P0 assigning %vreg83 to %VFLAG_P0: VFLAG_P0 [1496r,1624r:0) 0@1496r queuing new interval: %vreg78 [1360r,1512r:0) 0@1360r queuing new interval: %vreg87 [1536r,1672r:0) 0@1536r selectOrSplit VP0Regs:%vreg78 [1360r,1512r:0) 0@1360r w=1.140633e-02 RS_Assign Cascade 1 wait for second round queuing new interval: %vreg78 [1360r,1512r:0) 0@1360r selectOrSplit VP0Regs:%vreg87 [1536r,1672r:0) 0@1536r w=1.174682e-02 RS_Assign Cascade 1 wait for second round queuing new interval: %vreg87 [1536r,1672r:0) 0@1536r selectOrSplit VP0Regs:%vreg81 [1492r,1604r:0) 0@1492r w=1.229745e-02 RS_Assign Cascade 0 should evict: %vreg83 [1496r,1624r:0) 0@1496r w= 1.192480e-02 evicting %VFLAG_P0 interference: Cascade 2 unassigning %vreg83 from %VFLAG_P0: VFLAG_P0 assigning %vreg81 to %VFLAG_P0: VFLAG_P0 [1492r,1604r:0) 0@1492r queuing new interval: %vreg83 [1496r,1624r:0) 0@1496r selectOrSplit VP0Regs:%vreg83 [1496r,1624r:0) 0@1496r w=1.192480e-02 RS_Assign Cascade 2 wait for second round queuing new interval: %vreg83 [1496r,1624r:0) 0@1496r selectOrSplit VP0Regs:%vreg89 [1608r,1704r:0) 0@1608r w=1.269415e-02 assigning %vreg89 to %VFLAG_P0: VFLAG_P0 [1608r,1704r:0) 0@1608r selectOrSplit VP0Regs:%vreg75 [1328r,1400r:0) 0@1328r w=1.333961e-02 assigning %vreg75 to %VFLAG_P0: VFLAG_P0 [1328r,1400r:0) 0@1328r selectOrSplit FlagRegs:%vreg93 [1696r,1760r:0) 0@1696r w=1.356960e-02 AllocationOrder(FlagRegs) = [ %FLAG ] assigning %vreg93 to %FLAG: FLAG [1696r,1760r:0) 0@1696r selectOrSplit FlagRegs:%vreg132 [2768r,2832r:0) 0@2768r w=8.035334e-02 assigning %vreg132 to %FLAG: FLAG [2768r,2832r:0) 0@2768r selectOrSplit FlagRegs:%vreg24 [64r,80r:0) 0@64r w=4.807692e-03 assigning %vreg24 to %FLAG: FLAG [64r,80r:0) 0@64r selectOrSplit FlagRegs:%vreg26 [144r,176r:0) 0@144r w=2.914952e-03 assigning %vreg26 to %FLAG: FLAG [144r,176r:0) 0@144r selectOrSplit GRegs:%vreg28 [224r,240r:0) 0@224r w=INF assigning %vreg28 to %R3: R3 [224r,240r:0) 0@224r selectOrSplit FlagRegs:%vreg29 [256r,288r:0) 0@256r w=INF assigning %vreg29 to %FLAG: FLAG [256r,288r:0) 0@256r selectOrSplit GRegs:%vreg31 [336r,352r:0) 0@336r w=INF assigning %vreg31 to %R8: R8 [336r,352r:0) 0@336r selectOrSplit GRegs:%vreg32 [352r,368r:0) 0@352r w=INF assigning %vreg32 to %R8: R8 [352r,368r:0) 0@352r selectOrSplit FlagRegs:%vreg33 [368r,384r:0) 0@368r w=INF assigning %vreg33 to %FLAG: FLAG [368r,384r:0) 0@368r selectOrSplit GRegs:%vreg0 [432r,448r:0) 0@432r w=INF assigning %vreg0 to %R8: R8 [432r,448r:0) 0@432r selectOrSplit FlagRegs:%vreg34 [448r,480r:0) 0@448r w=INF assigning %vreg34 to %FLAG: FLAG [448r,480r:0) 0@448r selectOrSplit GRegs:%vreg37 [864r,880r:0) 0@864r w=1.528668e-02 assigning %vreg37 to %R14: R14 [864r,880r:0) 0@864r selectOrSplit VRegs:%vreg36 [872r,948r:0) 0@872r w=1.335979e-02 assigning %vreg36 to %V13: V13 [872r,948r:0) 0@872r selectOrSplit VRegs:%vreg39 [880r,952r:0) 0@880r w=1.347301e-02 assigning %vreg39 to %V14: V14 [880r,952r:0) 0@880r selectOrSplit GRegs:%vreg43 [944r,960r:0) 0@944r w=1.528668e-02 assigning %vreg43 to %R14: R14 [944r,960r:0) 0@944r selectOrSplit VRegs:%vreg35 [948r,1320r:0) 0@948r w=1.631165e-02 assigning %vreg35 to %V13: V13 [948r,1320r:0) 0@948r selectOrSplit VRegs:%vreg38 [952r,1048r:0) 0@952r w=1.269415e-02 assigning %vreg38 to %V14: V14 [952r,1048r:0) 0@952r selectOrSplit VRegs:%vreg45 [960r,976r:0) 0@960r w=1.528668e-02 assigning %vreg45 to %V15: V15 [960r,976r:0) 0@960r selectOrSplit VRegs:%vreg41 [968r,1096r:0) 0@968r w=1.788720e-02 assigning %vreg41 to %V16: V16 [968r,1096r:0) 0@968r selectOrSplit VRegs:%vreg44 [976r,1096r:0) 0@976r w=1.210826e-02 assigning %vreg44 to %V15: V15 [976r,1096r:0) 0@976r selectOrSplit VRegs:%vreg48 [1008r,1128r:0) 0@1008r w=1.210826e-02 assigning %vreg48 to %V17: V17 [1008r,1128r:0) 0@1008r selectOrSplit VRegs:%vreg51 [1040r,1256r:0) 0@1040r w=1.533189e-02 assigning %vreg51 to %V18: V18 [1040r,1256r:0) 0@1040r selectOrSplit VRegs:%vreg42 [1048r,1248r:0) 0@1048r w=1.574074e-02 assigning %vreg42 to %V14: V14 [1048r,1248r:0) 0@1048r selectOrSplit VRegs:%vreg55 [1088r,1176r:0) 0@1088r w=1.290225e-02 assigning %vreg55 to %V19: V19 [1088r,1176r:0) 0@1088r selectOrSplit VRegs:%vreg46 [1096r,1184r:0) 0@1096r w=1.935337e-02 assigning %vreg46 to %V15: V15 [1096r,1184r:0) 0@1096r selectOrSplit VRegs:%vreg58 [1120r,1192r:0) 0@1120r w=1.333961e-02 assigning %vreg58 to %V16: V16 [1120r,1192r:0) 0@1120r selectOrSplit VRegs:%vreg49 [1128r,1240r:0) 0@1128r w=1.229745e-02 assigning %vreg49 to %V17: V17 [1128r,1240r:0) 0@1128r selectOrSplit VRegs:%vreg62 [1168r,1184r:0) 0@1168r w=1.513533e-02 assigning %vreg62 to %V20: V20 [1168r,1184r:0) 0@1168r selectOrSplit VRegs:%vreg56 [1176r,1192r:0) 0@1176r w=1.513533e-02 assigning %vreg56 to %V19: V19 [1176r,1192r:0) 0@1176r selectOrSplit VRegs:%vreg63 [1184r,1256r:0) 0@1184r w=1.333961e-02 assigning %vreg63 to %V15: V15 [1184r,1256r:0) 0@1184r selectOrSplit VRegs:%vreg59 [1192r,1288r:0) 0@1192r w=1.269415e-02 assigning %vreg59 to %V16: V16 [1192r,1288r:0) 0@1192r selectOrSplit VRegs:%vreg67 [1232r,1248r:0) 0@1232r w=1.513533e-02 assigning %vreg67 to %V19: V19 [1232r,1248r:0) 0@1232r selectOrSplit VRegs:%vreg52 [1240r,1272r:0) 0@1240r w=1.457476e-02 assigning %vreg52 to %V17: V17 [1240r,1272r:0) 0@1240r selectOrSplit VRegs:%vreg68 [1248r,1280r:0) 0@1248r w=1.457476e-02 assigning %vreg68 to %V14: V14 [1248r,1280r:0) 0@1248r selectOrSplit VRegs:%vreg64 [1256r,1316r:0) 0@1256r w=1.368760e-02 assigning %vreg64 to %V15: V15 [1256r,1316r:0) 0@1256r selectOrSplit VRegs:%vreg70 [1264r,1280r:0) 0@1264r w=1.513533e-02 assigning %vreg70 to %V18: V18 [1264r,1280r:0) 0@1264r selectOrSplit VRegs:%vreg53 [1272r,1400r:0) 0@1272r w=2.384961e-02 assigning %vreg53 to %V17: V17 [1272r,1400r:0) 0@1272r selectOrSplit VRegs:%vreg71 [1280r,1320r:0) 0@1280r w=1.430976e-02 assigning %vreg71 to %V14: V14 [1280r,1320r:0) 0@1280r selectOrSplit VRegs:%vreg60 [1288r,1316r:0) 0@1288r w=1.471097e-02 assigning %vreg60 to %V16: V16 [1288r,1316r:0) 0@1288r selectOrSplit VRegs:%vreg74 [1312r,1672r:0) 0@1312r w=2.899610e-02 assigning %vreg74 to %V18: V18 [1312r,1672r:0) 0@1312r selectOrSplit VRegs:%vreg65 [1316r,1604r:0) 0@1316r w=1.830319e-02 assigning %vreg65 to %V15: V15 [1316r,1604r:0) 0@1316r selectOrSplit VRegs:%vreg72 [1320r,1672r:0) 0@1320r w=1.674547e-02 assigning %vreg72 to %V13: V13 [1320r,1672r:0) 0@1320r selectOrSplit VRegs:%vreg80 [1392r,1544r:0) 0@1392r w=1.152040e-02 assigning %vreg80 to %V14: V14 [1392r,1544r:0) 0@1392r selectOrSplit VRegs:%vreg76 [1400r,1512r:0) 0@1400r w=1.229745e-02 assigning %vreg76 to %V16: V16 [1400r,1512r:0) 0@1400r selectOrSplit GRegs:%vreg85 [1488r,1504r:0) 0@1488r w=1.528668e-02 assigning %vreg85 to %R14: R14 [1488r,1504r:0) 0@1488r selectOrSplit VRegs:%vreg86 [1504r,1656r:0) 0@1504r w=1.152040e-02 assigning %vreg86 to %V17: V17 [1504r,1656r:0) 0@1504r selectOrSplit VRegs:%vreg79 [1512r,1544r:0) 0@1512r w=1.457476e-02 assigning %vreg79 to %V16: V16 [1512r,1544r:0) 0@1512r selectOrSplit GRegs:%vreg91 [1600r,1616r:0) 0@1600r w=1.528668e-02 assigning %vreg91 to %R14: R14 [1600r,1616r:0) 0@1600r selectOrSplit VRegs:%vreg82 [1604r,1624r:0) 0@1604r w=1.499118e-02 assigning %vreg82 to %V14: V14 [1604r,1624r:0) 0@1604r selectOrSplit VRegs:%vreg92 [1616r,1720r:0) 0@1616r w=1.261758e-02 assigning %vreg92 to %V15: V15 [1616r,1720r:0) 0@1616r selectOrSplit VRegs:%vreg84 [1624r,1656r:0) 0@1624r w=1.457476e-02 assigning %vreg84 to %V14: V14 [1624r,1656r:0) 0@1624r selectOrSplit VRegs:%vreg88 [1672r,1704r:0) 0@1672r w=1.457476e-02 assigning %vreg88 to %V13: V13 [1672r,1704r:0) 0@1672r selectOrSplit VRegs:%vreg90 [1704r,1720r:0) 0@1704r w=1.513533e-02 assigning %vreg90 to %V13: V13 [1704r,1720r:0) 0@1704r selectOrSplit FlagRegs:%vreg94 [1808r,1840r:0) 0@1808r w=4.000915e-04 assigning %vreg94 to %FLAG: FLAG [1808r,1840r:0) 0@1808r selectOrSplit GRegs:%vreg95 [1936r,1976r:0) 0@1936r w=2.637486e-03 assigning %vreg95 to %R8: R8 [1936r,1976r:0) 0@1936r selectOrSplit GRegs:%vreg96 [1968r,1984r:0) 0@1968r w=2.789649e-03 assigning %vreg96 to %R1: R1 [1968r,1984r:0) 0@1968r selectOrSplit GRegs:%vreg97 [2112r,2196r:0) 0@2112r w=7.703295e-02 assigning %vreg97 to %R1: R1 [2112r,2196r:0) 0@2112r selectOrSplit GRegs:%vreg99 [2144r,2200r:0) 0@2144r w=8.176305e-02 assigning %vreg99 to %R2: R2 [2144r,2200r:0) 0@2144r selectOrSplit GRegs:%vreg102 [2192r,2208r:0) 0@2192r w=8.962488e-02 assigning %vreg102 to %R13: R13 [2192r,2208r:0) 0@2192r selectOrSplit GRegs:%vreg98 [2196r,2568r:0) 0@2196r w=9.659055e-02 assigning %vreg98 to %R1: R1 [2196r,2568r:0) 0@2196r selectOrSplit GRegs:%vreg100 [2200r,2216r:0) 0@2200r w=8.962488e-02 assigning %vreg100 to %R2: R2 [2200r,2216r:0) 0@2200r selectOrSplit GRegs:%vreg103 [2208r,2224r:0) 0@2208r w=8.962488e-02 assigning %vreg103 to %R13: R13 [2208r,2224r:0) 0@2208r selectOrSplit GRegs:%vreg101 [2216r,2384r:0) 0@2216r w=9.846114e-02 assigning %vreg101 to %R2: R2 [2216r,2384r:0) 0@2216r selectOrSplit GRegs:%vreg104 [2224r,2336r:0) 0@2224r w=1.092303e-01 assigning %vreg104 to %R13: R13 [2224r,2336r:0) 0@2224r selectOrSplit GRegs:%vreg105 [2240r,2296r:0) 0@2240r w=8.176305e-02 assigning %vreg105 to %R14: R14 [2240r,2296r:0) 0@2240r selectOrSplit GRegs:%vreg108 [2288r,2304r:0) 0@2288r w=8.962488e-02 assigning %vreg108 to %R15: R15 [2288r,2304r:0) 0@2288r selectOrSplit GRegs:%vreg106 [2296r,2344r:0) 0@2296r w=8.322310e-02 assigning %vreg106 to %R14: R14 [2296r,2344r:0) 0@2296r selectOrSplit GRegs:%vreg109 [2304r,2360r:0) 0@2304r w=8.176305e-02 assigning %vreg109 to %R15: R15 [2304r,2360r:0) 0@2304r selectOrSplit GRegs:%vreg111 [2336r,2352r:0) 0@2336r w=8.962488e-02 assigning %vreg111 to %R13: R13 [2336r,2352r:0) 0@2336r selectOrSplit GRegs:%vreg107 [2344r,2464r:0) 0@2344r w=1.433998e-01 assigning %vreg107 to %R14: R14 [2344r,2464r:0) 0@2344r selectOrSplit GRegs:%vreg112 [2352r,2392r:0) 0@2352r w=8.473625e-02 assigning %vreg112 to %R13: R13 [2352r,2392r:0) 0@2352r selectOrSplit GRegs:%vreg110 [2360r,2392r:0) 0@2360r w=8.630544e-02 assigning %vreg110 to %R15: R15 [2360r,2392r:0) 0@2360r selectOrSplit GRegs:%vreg114 [2384r,2400r:0) 0@2384r w=8.962488e-02 assigning %vreg114 to %R2: R2 [2384r,2400r:0) 0@2384r selectOrSplit GRegs:%vreg113 [2392r,2560r:0) 0@2392r w=1.312815e-01 assigning %vreg113 to %R13: R13 [2392r,2560r:0) 0@2392r selectOrSplit GRegs:%vreg115 [2400r,2568r:0) 0@2400r w=6.564075e-02 assigning %vreg115 to %R2: R2 [2400r,2568r:0) 0@2400r selectOrSplit FlagRegs:%vreg117 [2432r,2448r:0) 0@2432r w=INF assigning %vreg117 to %FLAG: FLAG [2432r,2448r:0) 0@2432r selectOrSplit GRegs:%vreg118 [2448r,2504r:0) 0@2448r w=8.176305e-02 assigning %vreg118 to %R15: R15 [2448r,2504r:0) 0@2448r selectOrSplit FlagRegs:%vreg119 [2464r,2504r:0) 0@2464r w=8.473625e-02 assigning %vreg119 to %FLAG: FLAG [2464r,2504r:0) 0@2464r selectOrSplit GRegs:%vreg121 [2496r,2536r:0) 0@2496r w=8.473625e-02 assigning %vreg121 to %R14: R14 [2496r,2536r:0) 0@2496r selectOrSplit GRegs:%vreg120 [2504r,2536r:0) 0@2504r w=8.630544e-02 assigning %vreg120 to %R15: R15 [2504r,2536r:0) 0@2504r selectOrSplit FlagRegs:%vreg122 [2528r,2544r:0) 0@2528r w=8.962488e-02 assigning %vreg122 to %FLAG: FLAG [2528r,2544r:0) 0@2528r selectOrSplit GRegs:%vreg123 [2544r,2576r:0) 0@2544r w=8.630544e-02 assigning %vreg123 to %R14: R14 [2544r,2576r:0) 0@2544r selectOrSplit FlagRegs:%vreg124 [2560r,2576r:0) 0@2560r w=8.962488e-02 assigning %vreg124 to %FLAG: FLAG [2560r,2576r:0) 0@2560r selectOrSplit GRegs:%vreg116 [2568r,2696r:0) 0@2568r w=1.412271e-01 assigning %vreg116 to %R1: R1 [2568r,2696r:0) 0@2568r selectOrSplit GRegs:%vreg125 [2576r,2632r:0) 0@2576r w=8.176305e-02 assigning %vreg125 to %R2: R2 [2576r,2632r:0) 0@2576r selectOrSplit GRegs:%vreg126 [2592r,2632r:0) 0@2592r w=8.473625e-02 assigning %vreg126 to %R13: R13 [2592r,2632r:0) 0@2592r selectOrSplit FlagRegs:%vreg127 [2624r,2640r:0) 0@2624r w=8.962488e-02 assigning %vreg127 to %FLAG: FLAG [2624r,2640r:0) 0@2624r selectOrSplit GRegs:%vreg128 [2640r,2728r:0) 0@2640r w=7.640154e-02 assigning %vreg128 to %R2: R2 [2640r,2728r:0) 0@2640r selectOrSplit GRegs:%vreg131 [2688r,2776r:0) 0@2688r w=7.640154e-02 assigning %vreg131 to %R13: R13 [2688r,2776r:0) 0@2688r selectOrSplit FlagRegs:%vreg129 [2696r,2728r:0) 0@2696r w=8.630544e-02 assigning %vreg129 to %FLAG: FLAG [2696r,2728r:0) 0@2696r selectOrSplit GRegs:%vreg130 [2728r,2776r:0) 0@2728r w=8.322310e-02 assigning %vreg130 to %R1: R1 [2728r,2776r:0) 0@2728r selectOrSplit VP0Regs:%vreg78 [1360r,1512r:0) 0@1360r w=1.140633e-02 RS_Split Cascade 1 Analyze counted 2 instrs in 1 blocks, through 0 blocks. Inline spilling VP0Regs:%vreg78 [1360r,1512r:0) 0@1360r From original %vreg78 Merged spilled regs: SS#0 [1360r,1512r:0) 0@x spillAroundUses %vreg78 rewrite: 1360r %vreg140 = VSFGTSP0vv %vreg53, %vreg77; VP0Regs:%vreg140 VRegs:%vreg53,%vreg77 spill: reload: rewrite: 1512r %vreg79 = VCMOVvv %vreg141, %vreg76, %vreg77; VRegs:%vreg79,%vreg76,%vreg77 VP0Regs:%vreg141 # Machine code for function yuv2rgb_mod: NoPHIs, TracksLiveness Frame Objects: fi#0: size=4, align=4, at location [SP] Function Live Ins: %R5 in %vreg21, %R6 in %vreg22, %R7 in %vreg23 BB#0: derived from LLVM BB %entry Live Ins: %R5 %R6 %R7 %vreg23 = COPY %R7; GRegs:%vreg23 %vreg137 = COPY %R6; GRegs:%vreg137 %vreg24 = SFLTSri %vreg23, 1; FlagRegs:%vreg24 GRegs:%vreg23 %vreg138 = COPY %R5; GRegs:%vreg138 BF %vreg24, ; FlagRegs:%vreg24 J Successors according to CFG: BB#1(0x50000000 / 0x80000000 = 62.50%) BB#10(0x30000000 / 0x80000000 = 37.50%) BB#1: derived from LLVM BB %for.body.preheader Predecessors according to CFG: BB#0 %vreg26 = SFLTUri %vreg23, 8; FlagRegs:%vreg26 GRegs:%vreg23 %vreg136 = ORri %ZERO, 0; GRegs:%vreg136 BF %vreg26, ; FlagRegs:%vreg26 J Successors according to CFG: BB#8(0x40000000 / 0x80000000 = 50.00%) BB#2(0x40000000 / 0x80000000 = 50.00%) BB#2: derived from LLVM BB %min.iters.checked Predecessors according to CFG: BB#1 %vreg28 = ADDri %ZERO, -8; GRegs:%vreg28 %vreg1 = ANDrr %vreg23, %vreg28; GRegs:%vreg1,%vreg23,%vreg28 %vreg29 = SFEQri %vreg1, 0; FlagRegs:%vreg29 GRegs:%vreg1 BF %vreg29, ; FlagRegs:%vreg29 J Successors according to CFG: BB#8(0x30000000 / 0x80000000 = 37.50%) BB#3(0x50000000 / 0x80000000 = 62.50%) BB#3: derived from LLVM BB %vector.memcheck Predecessors according to CFG: BB#2 %vreg31 = MULri %vreg23, 12; GRegs:%vreg31,%vreg23 %vreg32 = ADDrr %vreg138, %vreg31; GRegs:%vreg32,%vreg138,%vreg31 %vreg33 = SFLEUrr %vreg32, %vreg138; FlagRegs:%vreg33 GRegs:%vreg32,%vreg138 BF %vreg33, ; FlagRegs:%vreg33 J Successors according to CFG: BB#4(0x60000000 / 0x80000000 = 75.00%) BB#5(0x20000000 / 0x80000000 = 25.00%) BB#4: derived from LLVM BB %vector.memcheck Predecessors according to CFG: BB#3 %vreg0 = SLLri %vreg23, 1; GRegs:%vreg0,%vreg23 %vreg34 = SFLTSrr %vreg0, %vreg23; FlagRegs:%vreg34 GRegs:%vreg0,%vreg23 BF %vreg34, ; FlagRegs:%vreg34 J Successors according to CFG: BB#8(0x55555555 / 0x80000000 = 66.67%) BB#5(0x2aaaaaab / 0x80000000 = 33.33%) BB#5: derived from LLVM BB %vector.body.preheader Predecessors according to CFG: BB#3 BB#4 %vreg2 = SLLri %vreg23, 3; GRegs:%vreg2,%vreg23 %vreg3 = SLLri %vreg23, 2; GRegs:%vreg3,%vreg23 %vreg40 = VADDvi %V0, ; VRegs:%vreg40 %vreg47 = VADDvi %V0, ; VRegs:%vreg47 %vreg50 = VADDvi %V0, ; VRegs:%vreg50 %vreg54 = VADDvi %V0, ; VRegs:%vreg54 %vreg57 = VADDvi %V0, ; VRegs:%vreg57 %vreg61 = VADDvi %V0, ; VRegs:%vreg61 %vreg66 = VADDvi %V0, ; VRegs:%vreg66 %vreg69 = VADDvi %V0, ; VRegs:%vreg69 %vreg133 = COPY %vreg137; GRegs:%vreg133,%vreg137 %vreg73 = VADDvi %V0, ; VRegs:%vreg73 %vreg77 = VADDvi %V0, 0; VRegs:%vreg77 %vreg134 = COPY %vreg138; GRegs:%vreg134,%vreg138 %vreg135 = COPY %vreg1; GRegs:%vreg135,%vreg1 Successors according to CFG: BB#6(?%) BB#6: derived from LLVM BB %vector.body Predecessors according to CFG: BB#5 BB#6 %vreg37 = ADDrr %vreg3, %vreg133; GRegs:%vreg37,%vreg3,%vreg133 %vreg36 = COPY %vreg133; VRegs:%vreg36 GRegs:%vreg133 %vreg39 = COPY %vreg37; VRegs:%vreg39 GRegs:%vreg37 %vreg43 = ADDrr %vreg2, %vreg133; GRegs:%vreg43,%vreg2,%vreg133 %vreg35 = VLW %vreg36, 0; VRegs:%vreg35,%vreg36 %vreg38 = VLW %vreg39, 0; VRegs:%vreg38,%vreg39 %vreg45 = COPY %vreg43; VRegs:%vreg45 GRegs:%vreg43 %vreg41 = VLW %vreg40, 0; VRegs:%vreg41,%vreg40 %vreg44 = VLW %vreg45, 0; VRegs:%vreg44,%vreg45 %vreg48 = VLW %vreg47, 0; VRegs:%vreg48,%vreg47 %vreg51 = VLW %vreg50, 0; VRegs:%vreg51,%vreg50 %vreg42 = VADDvv %vreg38, %vreg41; VRegs:%vreg42,%vreg38,%vreg41 %vreg55 = VLW %vreg54, 0; VRegs:%vreg55,%vreg54 %vreg46 = VADDvv %vreg44, %vreg41; VRegs:%vreg46,%vreg44,%vreg41 %vreg58 = VLW %vreg57, 0; VRegs:%vreg58,%vreg57 %vreg49 = VMULvv %vreg46, %vreg48; VRegs:%vreg49,%vreg46,%vreg48 %vreg62 = VLW %vreg61, 0; VRegs:%vreg62,%vreg61 %vreg56 = VMULvv %vreg42, %vreg55; VRegs:%vreg56,%vreg42,%vreg55 %vreg63 = VMULvv %vreg46, %vreg62; VRegs:%vreg63,%vreg46,%vreg62 %vreg59 = VSRAvv %vreg56, %vreg58; VRegs:%vreg59,%vreg56,%vreg58 %vreg67 = VLW %vreg66, 0; VRegs:%vreg67,%vreg66 %vreg52 = VSRAvv %vreg49, %vreg51; VRegs:%vreg52,%vreg49,%vreg51 %vreg68 = VMULvv %vreg42, %vreg67; VRegs:%vreg68,%vreg42,%vreg67 %vreg64 = VSRAvv %vreg63, %vreg51; VRegs:%vreg64,%vreg63,%vreg51 %vreg70 = VLW %vreg69, 0; VRegs:%vreg70,%vreg69 %vreg53 = VADDvv %vreg52, %vreg35; VRegs:%vreg53,%vreg52,%vreg35 %vreg71 = VSRAvv %vreg68, %vreg70; VRegs:%vreg71,%vreg68,%vreg70 %vreg60 = VSUB %vreg35, %vreg59; VRegs:%vreg60,%vreg35,%vreg59 %vreg74 = VLW %vreg73, 0; VRegs:%vreg74,%vreg73 %vreg65 = VSUB %vreg60, %vreg64; VRegs:%vreg65,%vreg60,%vreg64 %vreg72 = VADDvv %vreg71, %vreg35; VRegs:%vreg72,%vreg71,%vreg35 %vreg75 = VSFLTSP0vv %vreg53, %vreg74; VP0Regs:%vreg75 VRegs:%vreg53,%vreg74 %vreg140 = VSFGTSP0vv %vreg53, %vreg77; VP0Regs:%vreg140 VRegs:%vreg53,%vreg77 %vreg80 = COPY %vreg134; VRegs:%vreg80 GRegs:%vreg134 %vreg76 = VCMOVvv %vreg75, %vreg53, %vreg74; VRegs:%vreg76,%vreg53,%vreg74 VP0Regs:%vreg75 %vreg85 = ADDrr %vreg3, %vreg134; GRegs:%vreg85,%vreg3,%vreg134 %vreg81 = VSFLTSP0vv %vreg65, %vreg74; VP0Regs:%vreg81 VRegs:%vreg65,%vreg74 %vreg83 = VSFGTSP0vv %vreg65, %vreg77; VP0Regs:%vreg83 VRegs:%vreg65,%vreg77 %vreg86 = COPY %vreg85; VRegs:%vreg86 GRegs:%vreg85 %vreg79 = VCMOVvv %vreg141, %vreg76, %vreg77; VRegs:%vreg79,%vreg76,%vreg77 VP0Regs:%vreg141 %vreg87 = VSFLTSP0vv %vreg72, %vreg74; VP0Regs:%vreg87 VRegs:%vreg72,%vreg74 VSW %vreg79, %vreg80, 0; VRegs:%vreg79,%vreg80 %vreg91 = ADDrr %vreg2, %vreg134; GRegs:%vreg91,%vreg2,%vreg134 %vreg82 = VCMOVvv %vreg81, %vreg65, %vreg74; VRegs:%vreg82,%vreg65,%vreg74 VP0Regs:%vreg81 %vreg89 = VSFGTSP0vv %vreg72, %vreg77; VP0Regs:%vreg89 VRegs:%vreg72,%vreg77 %vreg92 = COPY %vreg91; VRegs:%vreg92 GRegs:%vreg91 %vreg84 = VCMOVvv %vreg83, %vreg82, %vreg77; VRegs:%vreg84,%vreg82,%vreg77 VP0Regs:%vreg83 %vreg135 = ADDri %vreg135, -8; GRegs:%vreg135 VSW %vreg84, %vreg86, 0; VRegs:%vreg84,%vreg86 %vreg134 = ADDri %vreg134, 32; GRegs:%vreg134 %vreg88 = VCMOVvv %vreg87, %vreg72, %vreg74; VRegs:%vreg88,%vreg72,%vreg74 VP0Regs:%vreg87 %vreg93 = SFNEri %vreg135, 0; FlagRegs:%vreg93 GRegs:%vreg135 %vreg90 = VCMOVvv %vreg89, %vreg88, %vreg77; VRegs:%vreg90,%vreg88,%vreg77 VP0Regs:%vreg89 %vreg133 = ADDri %vreg133, 32; GRegs:%vreg133 VSW %vreg90, %vreg92, 0; VRegs:%vreg90,%vreg92 BF %vreg93, ; FlagRegs:%vreg93 J Successors according to CFG: BB#7(0x04000000 / 0x80000000 = 3.12%) BB#6(0x7c000000 / 0x80000000 = 96.88%) BB#7: derived from LLVM BB %middle.block Predecessors according to CFG: BB#6 %vreg94 = SFEQrr %vreg1, %vreg23; FlagRegs:%vreg94 GRegs:%vreg1,%vreg23 %vreg136 = COPY %vreg1; GRegs:%vreg136,%vreg1 BF %vreg94, ; FlagRegs:%vreg94 J Successors according to CFG: BB#10(0x40000000 / 0x80000000 = 50.00%) BB#8(0x40000000 / 0x80000000 = 50.00%) BB#8: derived from LLVM BB %for.body.preheader103 Predecessors according to CFG: BB#1 BB#2 BB#4 BB#7 %vreg139 = SUB %vreg23, %vreg136; GRegs:%vreg139,%vreg23,%vreg136 %vreg12 = SLLri %vreg136, 2; GRegs:%vreg12,%vreg136 %vreg95 = SLLri %vreg23, 3; GRegs:%vreg95,%vreg23 %vreg96 = SLLri %vreg23, 2; GRegs:%vreg96,%vreg23 %vreg13 = ADDrr %vreg12, %vreg95; GRegs:%vreg13,%vreg12,%vreg95 %vreg14 = ADDrr %vreg12, %vreg96; GRegs:%vreg14,%vreg12,%vreg96 Successors according to CFG: BB#9(?%) BB#9: derived from LLVM BB %for.body Predecessors according to CFG: BB#8 BB#9 %vreg97 = ADDrr %vreg12, %vreg137; GRegs:%vreg97,%vreg12,%vreg137 %vreg99 = ADDrr %vreg14, %vreg137; GRegs:%vreg99,%vreg14,%vreg137 %vreg102 = ADDrr %vreg13, %vreg137; GRegs:%vreg102,%vreg13,%vreg137 %vreg98 = LW %vreg97, 0; mem:LD4[%sunkaddr49](tbaa=!2) GRegs:%vreg98,%vreg97 %vreg100 = LW %vreg99, 0; mem:LD4[%uglygep1415](tbaa=!2) GRegs:%vreg100,%vreg99 %vreg103 = LW %vreg102, 0; mem:LD4[%uglygep1213](tbaa=!2) GRegs:%vreg103,%vreg102 %vreg101 = ADDri %vreg100, -128; GRegs:%vreg101,%vreg100 %vreg104 = ADDri %vreg103, -128; GRegs:%vreg104,%vreg103 %vreg105 = MULri %vreg104, 359; GRegs:%vreg105,%vreg104 %vreg108 = MULri %vreg101, 11; GRegs:%vreg108,%vreg101 %vreg106 = SRAri %vreg105, 8; GRegs:%vreg106,%vreg105 %vreg109 = SRAri %vreg108, 5; GRegs:%vreg109,%vreg108 %vreg111 = MULri %vreg104, 183; GRegs:%vreg111,%vreg104 %vreg107 = ADDrr %vreg106, %vreg98; GRegs:%vreg107,%vreg106,%vreg98 %vreg112 = SRAri %vreg111, 8; GRegs:%vreg112,%vreg111 %vreg110 = SUB %vreg98, %vreg109; GRegs:%vreg110,%vreg98,%vreg109 %vreg114 = MULri %vreg101, 227; GRegs:%vreg114,%vreg101 %vreg113 = SUB %vreg110, %vreg112; GRegs:%vreg113,%vreg110,%vreg112 %vreg115 = SRAri %vreg114, 7; GRegs:%vreg115,%vreg114 %vreg117 = SFLTSri %vreg107, 255; FlagRegs:%vreg117 GRegs:%vreg107 %vreg118 = CMOVri %vreg117, %vreg107, 255; GRegs:%vreg118,%vreg107 FlagRegs:%vreg117 %vreg119 = SFGTSri %vreg107, 0; FlagRegs:%vreg119 GRegs:%vreg107 %vreg121 = ADDrr %vreg12, %vreg138; GRegs:%vreg121,%vreg12,%vreg138 %vreg120 = CMOVri %vreg119, %vreg118, 0; GRegs:%vreg120,%vreg118 FlagRegs:%vreg119 %vreg122 = SFLTSri %vreg113, 255; FlagRegs:%vreg122 GRegs:%vreg113 SW %vreg120, %vreg121, 0; mem:ST4[%sunkaddr52](tbaa=!2) GRegs:%vreg120,%vreg121 %vreg123 = CMOVri %vreg122, %vreg113, 255; GRegs:%vreg123,%vreg113 FlagRegs:%vreg122 %vreg124 = SFGTSri %vreg113, 0; FlagRegs:%vreg124 GRegs:%vreg113 %vreg116 = ADDrr %vreg115, %vreg98; GRegs:%vreg116,%vreg115,%vreg98 %vreg125 = CMOVri %vreg124, %vreg123, 0; GRegs:%vreg125,%vreg123 FlagRegs:%vreg124 %vreg126 = ADDrr %vreg14, %vreg138; GRegs:%vreg126,%vreg14,%vreg138 %vreg127 = SFLTSri %vreg116, 255; FlagRegs:%vreg127 GRegs:%vreg116 SW %vreg125, %vreg126, 0; mem:ST4[%uglygep56](tbaa=!2) GRegs:%vreg125,%vreg126 %vreg128 = CMOVri %vreg127, %vreg116, 255; GRegs:%vreg128,%vreg116 FlagRegs:%vreg127 %vreg131 = ADDrr %vreg13, %vreg138; GRegs:%vreg131,%vreg13,%vreg138 %vreg129 = SFGTSri %vreg116, 0; FlagRegs:%vreg129 GRegs:%vreg116 %vreg139 = ADDri %vreg139, -1; GRegs:%vreg139 %vreg130 = CMOVri %vreg129, %vreg128, 0; GRegs:%vreg130,%vreg128 FlagRegs:%vreg129 %vreg138 = ADDri %vreg138, 4; GRegs:%vreg138 %vreg132 = SFNEri %vreg139, 0; FlagRegs:%vreg132 GRegs:%vreg139 %vreg137 = ADDri %vreg137, 4; GRegs:%vreg137 SW %vreg130, %vreg131, 0; mem:ST4[%uglygep4](tbaa=!2) GRegs:%vreg130,%vreg131 BF %vreg132, ; FlagRegs:%vreg132 J Successors according to CFG: BB#10(0x04000000 / 0x80000000 = 3.12%) BB#9(0x7c000000 / 0x80000000 = 96.88%) BB#10: derived from LLVM BB %for.end Predecessors according to CFG: BB#0 BB#7 BB#9 RetLR # End machine code for function yuv2rgb_mod. *** Bad machine code: Reading virtual register without a def *** - function: yuv2rgb_mod - basic block: BB#6 vector.body (0x7ff01000c948) - instruction: %vreg79 = VCMOVvv - operand 1: %vreg141 LLVM ERROR: Found 1 machine code errors. make: *** [out] Error 1