# Machine code for function yuv2rgb_mod: NoPHIs, TracksLiveness
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
Function Live Ins: %R5 in %vreg21, %R6 in %vreg22, %R7 in %vreg23

BB#0: derived from LLVM BB %entry
    Live Ins: %R5 %R6 %R7
	%vreg23<def> = COPY %R7; GRegs:%vreg23
	%vreg24<def> = SFLTSri %vreg23, 1; FlagRegs:%vreg24 GRegs:%vreg23
	%vreg137<def> = COPY %R6; GRegs:%vreg137
	%vreg138<def> = COPY %R5; GRegs:%vreg138
	BF %vreg24, <BB#10>; FlagRegs:%vreg24
	J <BB#1>
    Successors according to CFG: BB#1(0x50000000 / 0x80000000 = 62.50%) BB#10(0x30000000 / 0x80000000 = 37.50%)

BB#1: derived from LLVM BB %for.body.preheader
    Predecessors according to CFG: BB#0
	%vreg26<def> = SFLTUri %vreg23, 8; FlagRegs:%vreg26 GRegs:%vreg23
	%vreg136<def> = ORri %ZERO, 0; GRegs:%vreg136
	BF %vreg26, <BB#8>; FlagRegs:%vreg26
	J <BB#2>
    Successors according to CFG: BB#8(0x40000000 / 0x80000000 = 50.00%) BB#2(0x40000000 / 0x80000000 = 50.00%)

BB#2: derived from LLVM BB %min.iters.checked
    Predecessors according to CFG: BB#1
	%vreg28<def> = ADDri %ZERO, -8; GRegs:%vreg28
	%vreg1<def> = ANDrr %vreg23, %vreg28; GRegs:%vreg1,%vreg23,%vreg28
	%vreg29<def> = SFEQri %vreg1, 0; FlagRegs:%vreg29 GRegs:%vreg1
	BF %vreg29, <BB#8>; FlagRegs:%vreg29
	J <BB#3>
    Successors according to CFG: BB#8(0x30000000 / 0x80000000 = 37.50%) BB#3(0x50000000 / 0x80000000 = 62.50%)

BB#3: derived from LLVM BB %vector.memcheck
    Predecessors according to CFG: BB#2
	%vreg31<def> = MULri %vreg23, 12; GRegs:%vreg31,%vreg23
	%vreg32<def> = ADDrr %vreg138, %vreg31; GRegs:%vreg32,%vreg138,%vreg31
	%vreg33<def> = SFLEUrr %vreg32, %vreg138; FlagRegs:%vreg33 GRegs:%vreg32,%vreg138
	BF %vreg33, <BB#5>; FlagRegs:%vreg33
	J <BB#4>
    Successors according to CFG: BB#4(0x60000000 / 0x80000000 = 75.00%) BB#5(0x20000000 / 0x80000000 = 25.00%)

BB#4: derived from LLVM BB %vector.memcheck
    Predecessors according to CFG: BB#3
	%vreg0<def> = SLLri %vreg23, 1; GRegs:%vreg0,%vreg23
	%vreg34<def> = SFLTSrr %vreg0, %vreg23; FlagRegs:%vreg34 GRegs:%vreg0,%vreg23
	BF %vreg34, <BB#8>; FlagRegs:%vreg34
	J <BB#5>
    Successors according to CFG: BB#8(0x55555555 / 0x80000000 = 66.67%) BB#5(0x2aaaaaab / 0x80000000 = 33.33%)

BB#5: derived from LLVM BB %vector.body.preheader
    Predecessors according to CFG: BB#3 BB#4
	%vreg133<def> = COPY %vreg137; GRegs:%vreg133,%vreg137
	%vreg77<def> = VADDvi %V0, 0; VRegs:%vreg77
	%vreg73<def> = VADDvi %V0, <ga:@_PromotedVect.8>; VRegs:%vreg73
	%vreg69<def> = VADDvi %V0, <ga:@_PromotedVect.7>; VRegs:%vreg69
	%vreg66<def> = VADDvi %V0, <ga:@_PromotedVect.6>; VRegs:%vreg66
	%vreg61<def> = VADDvi %V0, <ga:@_PromotedVect.5>; VRegs:%vreg61
	%vreg57<def> = VADDvi %V0, <ga:@_PromotedVect.4>; VRegs:%vreg57
	%vreg54<def> = VADDvi %V0, <ga:@_PromotedVect.3>; VRegs:%vreg54
	%vreg50<def> = VADDvi %V0, <ga:@_PromotedVect.2>; VRegs:%vreg50
	%vreg47<def> = VADDvi %V0, <ga:@_PromotedVect.1>; VRegs:%vreg47
	%vreg40<def> = VADDvi %V0, <ga:@_PromotedVect>; VRegs:%vreg40
	%vreg3<def> = SLLri %vreg23, 2; GRegs:%vreg3,%vreg23
	%vreg2<def> = SLLri %vreg23, 3; GRegs:%vreg2,%vreg23
	%vreg134<def> = COPY %vreg138; GRegs:%vreg134,%vreg138
	%vreg135<def> = COPY %vreg1; GRegs:%vreg135,%vreg1
    Successors according to CFG: BB#6(?%)

BB#6: derived from LLVM BB %vector.body
    Predecessors according to CFG: BB#5 BB#6
	%vreg36<def> = COPY %vreg133; VRegs:%vreg36 GRegs:%vreg133
	%vreg37<def> = ADDrr %vreg3, %vreg133; GRegs:%vreg37,%vreg3,%vreg133
	%vreg35<def> = VLW %vreg36, 0; VRegs:%vreg35,%vreg36
	%vreg39<def> = COPY %vreg37; VRegs:%vreg39 GRegs:%vreg37
	%vreg38<def> = VLW %vreg39, 0; VRegs:%vreg38,%vreg39
	%vreg41<def> = VLW %vreg40, 0; VRegs:%vreg41,%vreg40
	%vreg43<def> = ADDrr %vreg2, %vreg133; GRegs:%vreg43,%vreg2,%vreg133
	%vreg42<def> = VADDvv %vreg38, %vreg41; VRegs:%vreg42,%vreg38,%vreg41
	%vreg45<def> = COPY %vreg43; VRegs:%vreg45 GRegs:%vreg43
	%vreg44<def> = VLW %vreg45, 0; VRegs:%vreg44,%vreg45
	%vreg48<def> = VLW %vreg47, 0; VRegs:%vreg48,%vreg47
	%vreg51<def> = VLW %vreg50, 0; VRegs:%vreg51,%vreg50
	%vreg55<def> = VLW %vreg54, 0; VRegs:%vreg55,%vreg54
	%vreg58<def> = VLW %vreg57, 0; VRegs:%vreg58,%vreg57
	%vreg62<def> = VLW %vreg61, 0; VRegs:%vreg62,%vreg61
	%vreg67<def> = VLW %vreg66, 0; VRegs:%vreg67,%vreg66
	%vreg70<def> = VLW %vreg69, 0; VRegs:%vreg70,%vreg69
	%vreg68<def> = VMULvv %vreg42, %vreg67; VRegs:%vreg68,%vreg42,%vreg67
	%vreg71<def> = VSRAvv %vreg68, %vreg70; VRegs:%vreg71,%vreg68,%vreg70
	%vreg46<def> = VADDvv %vreg44, %vreg41; VRegs:%vreg46,%vreg44,%vreg41
	%vreg72<def> = VADDvv %vreg71, %vreg35; VRegs:%vreg72,%vreg71,%vreg35
	%vreg49<def> = VMULvv %vreg46, %vreg48; VRegs:%vreg49,%vreg46,%vreg48
	%vreg140<def,dead> = VSFGTSP0vv %vreg72, %vreg77; VP0Regs:%vreg140 VRegs:%vreg72,%vreg77
	%vreg52<def> = VSRAvv %vreg49, %vreg51; VRegs:%vreg52,%vreg49,%vreg51
	%vreg56<def> = VMULvv %vreg42, %vreg55; VRegs:%vreg56,%vreg42,%vreg55
	%vreg53<def> = VADDvv %vreg52, %vreg35; VRegs:%vreg53,%vreg52,%vreg35
	%vreg59<def> = VSRAvv %vreg56, %vreg58; VRegs:%vreg59,%vreg56,%vreg58
	%vreg78<def> = VSFGTSP0vv %vreg53, %vreg77; VP0Regs:%vreg78 VRegs:%vreg53,%vreg77
	%vreg60<def> = VSUB %vreg35, %vreg59; VRegs:%vreg60,%vreg35,%vreg59
	%vreg63<def> = VMULvv %vreg46, %vreg62; VRegs:%vreg63,%vreg46,%vreg62
	%vreg74<def> = VLW %vreg73, 0; VRegs:%vreg74,%vreg73
	%vreg64<def> = VSRAvv %vreg63, %vreg51; VRegs:%vreg64,%vreg63,%vreg51
	%vreg75<def> = VSFLTSP0vv %vreg53, %vreg74; VP0Regs:%vreg75 VRegs:%vreg53,%vreg74
	%vreg65<def> = VSUB %vreg60, %vreg64; VRegs:%vreg65,%vreg60,%vreg64
	%vreg76<def> = VCMOVvv %vreg75, %vreg53, %vreg74; VRegs:%vreg76,%vreg53,%vreg74 VP0Regs:%vreg75
	%vreg81<def> = VSFLTSP0vv %vreg65, %vreg74; VP0Regs:%vreg81 VRegs:%vreg65,%vreg74
	%vreg79<def> = VCMOVvv %vreg78, %vreg76, %vreg77; VRegs:%vreg79,%vreg76,%vreg77 VP0Regs:%vreg78
	%vreg83<def> = VSFGTSP0vv %vreg65, %vreg77; VP0Regs:%vreg83 VRegs:%vreg65,%vreg77
	%vreg80<def> = COPY %vreg134; VRegs:%vreg80 GRegs:%vreg134
	VSW %vreg79, %vreg80, 0; VRegs:%vreg79,%vreg80
	%vreg82<def> = VCMOVvv %vreg81, %vreg65, %vreg74; VRegs:%vreg82,%vreg65,%vreg74 VP0Regs:%vreg81
	%vreg87<def> = VSFLTSP0vv %vreg72, %vreg74; VP0Regs:%vreg87 VRegs:%vreg72,%vreg74
	%vreg84<def> = VCMOVvv %vreg83, %vreg82, %vreg77; VRegs:%vreg84,%vreg82,%vreg77 VP0Regs:%vreg83
	%vreg85<def> = ADDrr %vreg3, %vreg134; GRegs:%vreg85,%vreg3,%vreg134
	%vreg91<def> = ADDrr %vreg2, %vreg134; GRegs:%vreg91,%vreg2,%vreg134
	%vreg86<def> = COPY %vreg85; VRegs:%vreg86 GRegs:%vreg85
	VSW %vreg84, %vreg86, 0; VRegs:%vreg84,%vreg86
	%vreg88<def> = VCMOVvv %vreg87, %vreg72, %vreg74; VRegs:%vreg88,%vreg72,%vreg74 VP0Regs:%vreg87
	%vreg92<def> = COPY %vreg91; VRegs:%vreg92 GRegs:%vreg91
	%vreg90<def> = VCMOVvv %vreg141, %vreg88, %vreg77; VRegs:%vreg90,%vreg88,%vreg77 VP0Regs:%vreg141
	%vreg135<def> = ADDri %vreg135, -8; GRegs:%vreg135
	VSW %vreg90, %vreg92, 0; VRegs:%vreg90,%vreg92
	%vreg93<def> = SFNEri %vreg135, 0; FlagRegs:%vreg93 GRegs:%vreg135
	%vreg134<def> = ADDri %vreg134, 32; GRegs:%vreg134
	%vreg133<def> = ADDri %vreg133, 32; GRegs:%vreg133
	BF %vreg93, <BB#6>; FlagRegs:%vreg93
	J <BB#7>
    Successors according to CFG: BB#7(0x04000000 / 0x80000000 = 3.12%) BB#6(0x7c000000 / 0x80000000 = 96.88%)

BB#7: derived from LLVM BB %middle.block
    Predecessors according to CFG: BB#6
	%vreg94<def> = SFEQrr %vreg1, %vreg23; FlagRegs:%vreg94 GRegs:%vreg1,%vreg23
	%vreg136<def> = COPY %vreg1; GRegs:%vreg136,%vreg1
	BF %vreg94, <BB#10>; FlagRegs:%vreg94
	J <BB#8>
    Successors according to CFG: BB#10(0x40000000 / 0x80000000 = 50.00%) BB#8(0x40000000 / 0x80000000 = 50.00%)

BB#8: derived from LLVM BB %for.body.preheader103
    Predecessors according to CFG: BB#1 BB#2 BB#4 BB#7
	%vreg139<def> = SUB %vreg23, %vreg136; GRegs:%vreg139,%vreg23,%vreg136
	%vreg95<def> = SLLri %vreg23, 3; GRegs:%vreg95,%vreg23
	%vreg12<def> = SLLri %vreg136, 2; GRegs:%vreg12,%vreg136
	%vreg96<def> = SLLri %vreg23, 2; GRegs:%vreg96,%vreg23
	%vreg13<def> = ADDrr %vreg12, %vreg95; GRegs:%vreg13,%vreg12,%vreg95
	%vreg14<def> = ADDrr %vreg12, %vreg96; GRegs:%vreg14,%vreg12,%vreg96
    Successors according to CFG: BB#9(?%)

BB#9: derived from LLVM BB %for.body
    Predecessors according to CFG: BB#8 BB#9
	%vreg99<def> = ADDrr %vreg14, %vreg137; GRegs:%vreg99,%vreg14,%vreg137
	%vreg100<def> = LW %vreg99, 0; mem:LD4[%uglygep1415](tbaa=!2) GRegs:%vreg100,%vreg99
	%vreg101<def> = ADDri %vreg100, -128; GRegs:%vreg101,%vreg100
	%vreg108<def> = MULri %vreg101, 11; GRegs:%vreg108,%vreg101
	%vreg102<def> = ADDrr %vreg13, %vreg137; GRegs:%vreg102,%vreg13,%vreg137
	%vreg109<def> = SRAri %vreg108, 5; GRegs:%vreg109,%vreg108
	%vreg103<def> = LW %vreg102, 0; mem:LD4[%uglygep1213](tbaa=!2) GRegs:%vreg103,%vreg102
	%vreg97<def> = ADDrr %vreg12, %vreg137; GRegs:%vreg97,%vreg12,%vreg137
	%vreg104<def> = ADDri %vreg103, -128; GRegs:%vreg104,%vreg103
	%vreg98<def> = LW %vreg97, 0; mem:LD4[%sunkaddr49](tbaa=!2) GRegs:%vreg98,%vreg97
	%vreg111<def> = MULri %vreg104, 183; GRegs:%vreg111,%vreg104
	%vreg110<def> = SUB %vreg98, %vreg109; GRegs:%vreg110,%vreg98,%vreg109
	%vreg112<def> = SRAri %vreg111, 8; GRegs:%vreg112,%vreg111
	%vreg105<def> = MULri %vreg104, 359; GRegs:%vreg105,%vreg104
	%vreg113<def> = SUB %vreg110, %vreg112; GRegs:%vreg113,%vreg110,%vreg112
	%vreg106<def> = SRAri %vreg105, 8; GRegs:%vreg106,%vreg105
	%vreg124<def> = SFGTSri %vreg113, 0; FlagRegs:%vreg124 GRegs:%vreg113
	%vreg107<def> = ADDrr %vreg106, %vreg98; GRegs:%vreg107,%vreg106,%vreg98
	%vreg122<def> = SFLTSri %vreg113, 255; FlagRegs:%vreg122 GRegs:%vreg113
	%vreg119<def> = SFGTSri %vreg107, 0; FlagRegs:%vreg119 GRegs:%vreg107
	%vreg117<def> = SFLTSri %vreg107, 255; FlagRegs:%vreg117 GRegs:%vreg107
	%vreg114<def> = MULri %vreg101, 227; GRegs:%vreg114,%vreg101
	%vreg118<def> = CMOVri %vreg117, %vreg107, 255; GRegs:%vreg118,%vreg107 FlagRegs:%vreg117
	%vreg115<def> = SRAri %vreg114, 7; GRegs:%vreg115,%vreg114
	%vreg120<def> = CMOVri %vreg119, %vreg118, 0; GRegs:%vreg120,%vreg118 FlagRegs:%vreg119
	%vreg116<def> = ADDrr %vreg115, %vreg98; GRegs:%vreg116,%vreg115,%vreg98
	%vreg121<def> = ADDrr %vreg12, %vreg138; GRegs:%vreg121,%vreg12,%vreg138
	SW %vreg120, %vreg121, 0; mem:ST4[%sunkaddr52](tbaa=!2) GRegs:%vreg120,%vreg121
	%vreg123<def> = CMOVri %vreg122, %vreg113, 255; GRegs:%vreg123,%vreg113 FlagRegs:%vreg122
	%vreg127<def> = SFLTSri %vreg116, 255; FlagRegs:%vreg127 GRegs:%vreg116
	%vreg125<def> = CMOVri %vreg124, %vreg123, 0; GRegs:%vreg125,%vreg123 FlagRegs:%vreg124
	%vreg129<def> = SFGTSri %vreg116, 0; FlagRegs:%vreg129 GRegs:%vreg116
	%vreg126<def> = ADDrr %vreg14, %vreg138; GRegs:%vreg126,%vreg14,%vreg138
	SW %vreg125, %vreg126, 0; mem:ST4[%uglygep56](tbaa=!2) GRegs:%vreg125,%vreg126
	%vreg128<def> = CMOVri %vreg127, %vreg116, 255; GRegs:%vreg128,%vreg116 FlagRegs:%vreg127
	%vreg131<def> = ADDrr %vreg13, %vreg138; GRegs:%vreg131,%vreg13,%vreg138
	%vreg130<def> = CMOVri %vreg129, %vreg128, 0; GRegs:%vreg130,%vreg128 FlagRegs:%vreg129
	%vreg139<def> = ADDri %vreg139, -1; GRegs:%vreg139
	SW %vreg130, %vreg131, 0; mem:ST4[%uglygep4](tbaa=!2) GRegs:%vreg130,%vreg131
	%vreg132<def> = SFNEri %vreg139, 0; FlagRegs:%vreg132 GRegs:%vreg139
	%vreg138<def> = ADDri %vreg138, 4; GRegs:%vreg138
	%vreg137<def> = ADDri %vreg137, 4; GRegs:%vreg137
	BF %vreg132, <BB#9>; FlagRegs:%vreg132
	J <BB#10>
    Successors according to CFG: BB#10(0x04000000 / 0x80000000 = 3.12%) BB#9(0x7c000000 / 0x80000000 = 96.88%)

BB#10: derived from LLVM BB %for.end
    Predecessors according to CFG: BB#0 BB#7 BB#9
	RetLR

# End machine code for function yuv2rgb_mod.

*** Bad machine code: Reading virtual register without a def ***
- function:    yuv2rgb_mod
- basic block: BB#6 vector.body (0x10600a140)
- instruction: %vreg90<def> = VCMOVvv
- operand 1:   %vreg141
LLVM ERROR: Found 1 machine code errors.
Program ended with exit code: 1