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<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Book Antiqua",serif">The CPU that I am targeting is VLIW with no hardware interlocking (the next instruction does not wait for the previous to complete). This leads to fairly complex scheduling,
but can be generally accommodated well in LLVM.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Book Antiqua",serif"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Book Antiqua",serif">However, I have a small number of useful instructions with quite complex scheduling interactions between latency, register liveness and which have more than one register as
input and more than one as output.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Book Antiqua",serif"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Book Antiqua",serif">LLVM assumes that input registers are read as an instruction commences and become dead at that time; while output registers are committed when the instruction latency is complete
and they become live at that time.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Book Antiqua",serif"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Book Antiqua",serif">But for some instructions this is not the case. I have one particular example of an instruction where one of the input registers is read and becomes dead as the instruction
starts, but the other input register is read and becomes dead at the commencement of the following cycle. It also writes-back one of the output registers at the end of the 2<sup>nd</sup> cycle which is when that register becomes truly live, and the other
output register is written-back 4 cycles later which is when it becomes live.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Book Antiqua",serif"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Book Antiqua",serif">The TableGen descriptions do not seem to have any means of binding a register-liveness schedule to specific operands.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Book Antiqua",serif"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Book Antiqua",serif">So far I have omitted supporting these particular instructions as I can’t figure out how they can be modelled within LLVM. Does anybody know how I might approach describing
these kind of semantics to LLVM so that I can safely schedule them?<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Book Antiqua",serif"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Book Antiqua",serif">Variations of this involve instructions designed for pipelined execution, and in pipelined mode then schedule for some operands is different than for single-issue execution.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Book Antiqua",serif"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Book Antiqua",serif">Thanks,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Book Antiqua",serif"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Book Antiqua",serif"> MartinO<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Book Antiqua",serif"><o:p> </o:p></span></p>
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