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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Hi Krzysztof,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Thanks a lot for taking the time to write a detailed explanation. I think I understand things better now.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">I am trying to see if I can use RDF for X86 assuming I can add more register units for X86 so that the partial re-definition issue you pointed earlier is fixed.
I am not yet sure whether it is easy or not, but I have identified a portion of code in TableGen which I can modify to do this.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Once I have done this I plan to use the RDG graph construction and RDF copy propagation code to try to propagate copies in the code after RA.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">I am hoping that this plan would work.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Regards,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Venu.<o:p></o:p></span></p>
<div>
<div>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal">From: <b>Krzysztof Parzyszek via llvm-dev</b> <<a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a>><br>
Date: Mon, Oct 30, 2017 at 7:25 PM<br>
Subject: Re: [llvm-dev] Reaching definitions on Machine IR post register allocation<br>
To: <a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a><br>
<br>
<br>
Hi Raghavan,<br>
Thanks for asking the questions, it's not a problem at all.<br>
<br>
The RDF graph simulates SSA. It does so by having "artificial" PHI nodes that account for multiple reaching defs.<br>
<br>
Consider this example (for Hexagon). The CFG is a simple triangle which has a split block (BB#0), which either goes to the side block (BB#1), or to the join block (BB#2). The register R0 is defined in BB#0 and then redefined in BB#1. Both definitions can reach
the use of R0 in BB#2:<br>
<br>
<br>
***<br>
Before Hexagon RDF optimizations<br>
# Machine code for function fred: IsSSA, NoPHIs, TracksLiveness, NoVRegs<br>
<br>
BB#0:<br>
Live Ins: %P0<br>
%R0<def> = IMPLICIT_DEF<br>
J2_jumpt %P0, <BB#2>, %PC<imp-def> ; Conditional branch to BB#2<br>
Successors according to CFG: BB#1 BB#2<br>
<br>
BB#1:<br>
Predecessors according to CFG: BB#0<br>
%R0<def> = IMPLICIT_DEF<br>
Successors according to CFG: BB#2<br>
<br>
BB#2:<br>
Live Ins: %R0<br>
Predecessors according to CFG: BB#0 BB#1<br>
%R1<def> = COPY %R0<br>
***<br>
<br>
The constructed graph is below. Note the phi node (p17) in BB#2:<br>
<br>
Starting copy propagation on: fred<br>
DFG dump:[<br>
f1: Function: fred<br>
b2: --- BB#0 --- preds(0): succs(2): BB#1, BB#2<br>
p15: phi [+d16<P0>(,,u7):]<br>
s3: IMPLICIT_DEF [d4<R0>(,d10,u19):]<br>
s5: J2_jumpt BB#2 [/+d6<PC>!(,,):, u7<P0>(+d16):]<br>
<br>
b8: --- BB#1 --- preds(1): BB#0 succs(1): BB#2<br>
s9: IMPLICIT_DEF [d10<R0>(d4,,u20):]<br>
<br>
b11: --- BB#2 --- preds(2): BB#0, BB#1 succs(0):<br>
p17: phi [+d18<R0>(,,u14):, u19<R0>(d4,b2):, u20<R0>(d10,b8):] ; *PHI*<br>
s12: COPY [d13<R1>(,,):, u14<R0>(+d18):]<br>
<br>
]<br>
<br>
<br>
The phi node has uses which are linked to the reaching defs, and paired with the predecessor block to which the def corresponds. At this point, the graph looks a lot like the standard SSA graph.<br>
<br>
<br>
There are cases where there are multiple reaching defs emerging in a straight-line code. Imagine a register BIG_REG that has two non-overlapping subregisters, SMALL_REG_1 and SMALL_REG_2. Now, consider this:<br>
<br>
SMALL_REG_1 = ...<br>
SMALL_REG_2 = ...<br>
... = BIG_REG<br>
<br>
Both of the preceding definitions of of the subregisters of BIG_REG reach the use of BIG_REG, and both of them have to be connected to the use somehow. Phi nodes are not the solution, since they are specific to join blocks in the control flow graph. What RDF
does is that it adds additional uses of BIG_REG, and each of them has a different reaching def. These uses are called "shadows" in the RDF terminology.<br>
<br>
A concrete example (from Hexagon again, D0 is a pair of registers R0 and R1). Note the two uses u9 and u10 in the COPY instruction, and that each of them has one of the preceding defs as its reaching def:<br>
<br>
Before Hexagon RDF optimizations<br>
# Machine code for function fred: IsSSA, NoPHIs, TracksLiveness, NoVRegs<br>
<br>
BB#0:<br>
%R0<def> = IMPLICIT_DEF<br>
%R1<def> = IMPLICIT_DEF<br>
%D1<def> = COPY %D0<br>
<br>
# End machine code for function fred.<br>
<br>
Starting copy propagation on: fred<br>
DFG dump:[<br>
f1: Function: fred<br>
b2: --- BB#0 --- preds(0): succs(0):<br>
s3: IMPLICIT_DEF [d4<R0>(,,u10"):]<br>
s5: IMPLICIT_DEF [d6<R1>(,,u9"):]<br>
s7: COPY [d8<D1>(,,):, u9"<D0>(d6):, u10"<D0>(d4):] ;; Two uses: u9, u10<br>
<br>
]<br>
<br>
<br>
<br>
In the example above, the fact that the two subregisters were non-overlapping was important. If they are non-overlapping, there won't be any data-flow links between them, since they are essentially independent registers. If they were overlapping, such links
would be present. Here's a modified version of the example above, where we first modify D0, then one of its subregisters, and then read the whole D0:<br>
<br>
Before Hexagon RDF optimizations<br>
# Machine code for function fred: IsSSA, NoPHIs, TracksLiveness, NoVRegs<br>
<br>
BB#0:<br>
%D0<def> = IMPLICIT_DEF<br>
%R1<def> = IMPLICIT_DEF<br>
%D1<def> = COPY %D0<br>
<br>
# End machine code for function fred.<br>
<br>
Starting copy propagation on: fred<br>
DFG dump:[<br>
f1: Function: fred<br>
b2: --- BB#0 --- preds(0): succs(0):<br>
s3: IMPLICIT_DEF [d4<D0>(,d6,):]<br>
s5: IMPLICIT_DEF [d6<R1>(d4,,u9):]<br>
s7: COPY [d8<D1>(,,):, u9<D0>(d6):]<br>
<br>
]<br>
<br>
<br>
This time, the use of D0 only has the immediately preceding def of R1, and that def is then linked to the preceding def of D0.<br>
<br>
<br>
Before I describe how to get the reaching defs from the graph, let me point out that there is a function "getAllReachingDefs" in RDFLiveness.cpp that for a given RefNode returns the vector of all reaching defs from the same block in the order in which they
would be encountered going backwards from the RefNode to the beginning of the basic block. That function will only return defs from the same basic block as the RefNode is in. This function was meant to hide the complexity of finding reaching defs "by hand",
and is the preferred way of getting reaching defs.<br>
<br>
Now, to get all reaching defs for a given use or def, you need to follow the "reaching-def" link up in the graph, possibly multiple times, until the set of registers associated with these reaching defs covers the register from the use/def that you started from.
In the last example, there is a use of D0, and the reaching def is d6, which is associated with R1. The set {R1} does not cover D0, so you'd need to go further up, to the reaching def of d6. That def (d4) defines D0, so now the set of registers is {R1,D0},
which completely covers D0, so the algorithm stops: the list of reaching defs is d6, d4.<br>
All of that work is done by getAllReachingDefs, together with handling shadows and all other necessary cases.<br>
<br>
<br>
The "isPreserving" flag has more to do with making sure that all necessary links are present in the graph. The idea is that the entire data flow is completely represented via the links, and so the exact semantics of the machine instructions does not need to
be known.<br>
If you have two definitions of the same register following one another, and the first one does not reach any uses, it may be considered "dead" by looking at the data-flow links alone. If the second one is predicated, it may or may not happen, and so the preceding
def is not guaranteed to be dead (and cannot be removed). In other words, it can "preserve" the original value (or, in general, one or more bits of the original value), hence the name. I don't think that it's necessary to have that flag anymore (i.e. RDF can
be modified to work without it), but there are some historical reasons why it was introduced.<br>
<br>
-Krzysztof<o:p></o:p></p>
<div>
<div>
<p class="MsoNormal"><br>
<br>
<br>
On 10/30/2017 4:13 AM, Raghavan, Venugopal via llvm-dev wrote:<o:p></o:p></p>
<blockquote style="border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-right:0in">
<p class="MsoNormal" style="margin-bottom:12.0pt">Hi Krzysztof,<br>
<br>
I am returning to this thread after a gap in time. I took some time to study the code in RDFGraph.cpp in the Hexagon directory.<br>
<br>
I have a few questions. I hope you will not find it too much of a bother to answer them.<br>
<br>
1) Does use node only support a single reaching def? If the RDF graph is constructed post-RA, the code is no longer in SSA form and is it not possible that multiple reaching defs reach a use node? For example, the same physical register RAX may be defined in
the if branch and the else branch and can reach a common use node resulting in multiple reaching defs for a use node. How is this handled?<br>
2) I am unable to locate the code that handles re-definition of the same register. I though "clobber" refers to such situations but the isClobbering() function which controls the setting of the "Clobbering" attribute seems to mainly handle function calls and
not the re-definitions of registers through other types of instructions. How are such re-definitions handled?<br>
3) My mental picture of reaching definitions analysis is the classical iterative data flow analysis approach which involves using the union operator as the join operator for the data flow information, but I do not see anything in the code that corresponds to
such a notion. I am obviously way off the mark here, so, can you briefly explain the idea behind the reaching definitions analysis in the RDF code?<br>
4) Assuming I have somehow fixed the register units issue for x86 (which you mentioned in a previous reply) in the TableGen code by adding extra register units for x86, I am not sure how the preservation of the previous defined value through a partial over-write
by a sub-register definition is handled in the RDF code. I looked at the isPreserving() function but that function seems to check whether the instruction is predicated or not which is a little confusing to me since the x86 case can create preservation of bits
through non-predicated partial over-writes. So, how is the x86 situation handled?<br>
<br>
I realize that I have asked too many questions, but, I hope you can briefly provide me some clarifications.<br>
<br>
Thanks.<br>
<br>
Regards,<br>
Venugopal Raghavan.<br>
<br>
-----Original Message-----<br>
From: <a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a> [mailto:<a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a>]<br>
Sent: Tuesday, September 12, 2017 11:31 PM<br>
To: Raghavan, Venugopal <<a href="mailto:Venugopal.Raghavan@amd.com" target="_blank">Venugopal.Raghavan@amd.com</a>><br>
Cc: <a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a><br>
Subject: Re: [llvm-dev] Reaching definitions on Machine IR post register allocation<br>
<br>
Hi Venu,<o:p></o:p></p>
<blockquote style="border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-right:0in">
<p class="MsoNormal">On Sep 11, 2017, at 11:00 PM, Raghavan, Venugopal via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>> wrote:<br>
<br>
Hi Krzysztof,<br>
<br>
Thanks for your reply.<br>
<br>
I agree that adding extra register units for x86 would be the right way to fix this. Do you know if there is a plan to fix this?<o:p></o:p></p>
</blockquote>
<p class="MsoNormal" style="margin-bottom:12.0pt"><br>
No concrete plan, no. We've been thinking about for quite some time now, but never got at it.<br>
<br>
Cheers,<br>
-Quentin<o:p></o:p></p>
<blockquote style="border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-right:0in">
<p class="MsoNormal"><br>
The case that you have pointed out involving partial writes to a register together completely killing a wider register is interesting and did not occur to me. But, for reaching definitions, even if you do not detect this case, shouldn't this be safe (although
conservative) since you would only end up over-estimating the set of reaching definitions at a point?<br>
<br>
But for other scenarios such as copy propagation, you may need to detect this scenario because otherwise you could assume that a copy reaches a use point (when it actually does not) and you may end up propagating the copy when it is incorrect to do so.<br>
<br>
Regards,<br>
Venu.<br>
<br>
<br>
-----Original Message-----<br>
From: llvm-dev [mailto:<a href="mailto:llvm-dev-bounces@lists.llvm.org" target="_blank">llvm-dev-bounces@lists.llvm.org</a>] On Behalf Of<br>
Krzysztof Parzyszek via llvm-dev<br>
Sent: Friday, September 8, 2017 7:10 PM<br>
To: <a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a><br>
Subject: Re: [llvm-dev] Reaching definitions on Machine IR post<br>
register allocation<br>
<br>
It would be much easier to add extra reg units to EAX, EBX, etc. to represent the upper half of the register. That would fix the issue the right way (and would actually make sense without the context of RDF).<br>
<br>
Regarding the sub-register check---consider this case:<br>
<br>
AX = ...<br>
...<br>
AL = ... // AX partially overwritten<br>
AH = ... // AX completely overwritten<br>
<br>
Each of the assignments to AL/AH does not overwrite AX by itself, but together they do. This would be very difficult to detect if we added such special treatment of sub-registers that you propose.<br>
<br>
I could try to make a case for the extra register units to get them added.<br>
<br>
-Krzysztof<br>
<br>
<br>
On 9/8/2017 1:55 AM, Raghavan, Venugopal via llvm-dev wrote:<o:p></o:p></p>
<blockquote style="border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-right:0in">
<p class="MsoNormal">Hi Krzysztof,<br>
<br>
Thanks for your explanation - I think I understand the issue now.<br>
<br>
I do know if this is a hack, but, in reaching definitions, when we check if a definition of AX kills a previous definition of EAX, can we not check the actual physical register? In this case since EAX and AX are different (although I understand AX is a sub-register
of EAX), can we not conclude that the definition of AX does not kill EAX? Since, in reaching definitions, it is conservative if we over-estimate the set of reaching definitions (but not unsafe), should not this strategy be adequate to avoid incorrect optimizations?<br>
<br>
Or, is there an optimization that can behave incorrectly with an overestimated set of reaching definitions?<br>
<br>
Regards,<br>
Venu.<br>
<br>
-----Original Message-----<br>
From: Nema, Ashutosh<br>
Sent: Friday, September 08, 2017 12:00 PM<br>
To: Raghavan, Venugopal <<a href="mailto:Venugopal.Raghavan@amd.com" target="_blank">Venugopal.Raghavan@amd.com</a>><br>
Subject: FW: [llvm-dev] Reaching definitions on Machine IR post<br>
register allocation<br>
<br>
<br>
<br>
-----Original Message-----<br>
From: llvm-dev [mailto:<a href="mailto:llvm-dev-bounces@lists.llvm.org" target="_blank">llvm-dev-bounces@lists.llvm.org</a>] On Behalf Of<br>
Krzysztof Parzyszek via llvm-dev<br>
Sent: Wednesday, September 6, 2017 6:10 PM<br>
To: <a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a><br>
Subject: Re: [llvm-dev] Reaching definitions on Machine IR post<br>
register allocation<br>
<br>
RDF needs to know when an assignment to a register is overwritten by another assignment, or by a sequence of assignments. This is needed to determine whether the original assignment is still live or not. RDF uses register units to represent the building blocks
of registers, and assumes that if all units of a register are overwritten, then the original value of that register is completely overwritten. This assumption is true for all targets (that I have tested it with) except X86. On X86, registers AX and EAX both
have only one register unit, but when you assign a value to AX, the upper half of EAX is preserved (that is, the original value of EAX is not completely overwritten).<br>
<br>
-Krzysztof<br>
<br>
On 9/6/2017 6:42 AM, Raghavan, Venugopal via llvm-dev wrote:<o:p></o:p></p>
<blockquote style="border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-right:0in">
<p class="MsoNormal">Hi Krzysztof,<br>
<br>
I did look at the other link you have mentioned in your reply but did not quite understand the register units issue. If it is not too difficult, can you briefly summarize what the issue was?<br>
<br>
Thanks.<br>
<br>
Regards,<br>
Venu.<br>
<br>
<br>
-----Original Message-----<br>
From: llvm-dev [mailto:<a href="mailto:llvm-dev-bounces@lists.llvm.org" target="_blank">llvm-dev-bounces@lists.llvm.org</a>] On Behalf Of<br>
Krzysztof Parzyszek via llvm-dev<br>
Sent: Tuesday, September 5, 2017 7:44 PM<br>
To: <a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a><br>
Subject: Re: [llvm-dev] Reaching definitions on Machine IR post<br>
register allocation<br>
<br>
Hexagon has RDF that does exactly that. At the moment it's under lib/Target/Hexagon, but it meant to be target-independent. It won't work with X86 due to a known issue related to register units, but it should work fine for other targets. See
<a href="https://reviews.llvm.org/D29295" target="_blank">https://reviews.llvm.org/D29295</a> about moving it to lib/CodeGen.<br>
<br>
-Krzysztof<br>
<br>
On 9/4/2017 9:00 AM, Raghavan, Venugopal via llvm-dev wrote:<o:p></o:p></p>
<blockquote style="border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-right:0in">
<p class="MsoNormal" style="margin-bottom:12.0pt">Hi,<br>
<br>
Just to clarify I am looking for a whole machine function analysis<br>
not just something restricted to within a machine basic block.<br>
<br>
Thanks.<br>
<br>
Regards,<br>
<br>
Venu.<br>
<br>
*From:* Raghavan, Venugopal<br>
*Sent:* Saturday, September 02, 2017 12:56 PM<br>
*To:* <a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a><br>
*Subject:* Reaching definitions on Machine IR post register<br>
allocation<br>
<br>
Hi,<br>
<br>
Given a definition of a register by a machine instruction in the<br>
Machine IR post register allocation, I would like to compute the<br>
set of uses of this register reached by this definition.<br>
<br>
Does LLVM already have this kind of analysis I can use? Otherwise,<br>
I will have to implement a reaching definitions analysis which<br>
would be a little involved since it would need to work on a non-SSA IR form.<br>
<br>
If something already exists that would be very helpful for me.<br>
<br>
Thanks.<br>
<br>
Regards,<br>
<br>
Venugopal Raghavan.<br>
<br>
<br>
<br>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><br>
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</blockquote>
<p class="MsoNormal"><br>
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_______________________________________________<br>
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</blockquote>
<p class="MsoNormal"><br>
-- <br>
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation<br>
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LLVM Developers mailing list<br>
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<p class="MsoNormal"><br>
<br clear="all">
<o:p></o:p></p>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
</div>
<p class="MsoNormal">-- <o:p></o:p></p>
<div>
<p class="MsoNormal"><span style="font-size:13.5pt;font-family:"Comic Sans MS";color:#993399;background:white">Thanks & Regards</span><o:p></o:p></p>
<div>
<p class="MsoNormal"><span style="font-size:13.5pt;font-family:"Comic Sans MS";color:#993399;background:white">Deepali Rai</span><o:p></o:p></p>
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