<html><body><p><font size="2">Hi Jun,</font><br><br><font size="2">If we were to enable this by default, I think we'd make a push to enable it with or without PGO. I'm not sure what's currently preventing the partial inlining pass to be enabled by default, actually. David Li may have a better sense on this as he's been actively working on it most recently.</font><br><br><font size="2">As for the cost model, right now it's platform independent, so I'm assuming you'll need some sort of hook for platform-specific costs/bonuses to detect spilling of different types of registers. Also, I'm not quite sure how you'll do this type of detection at the IR level. Are you thinking some sort of heuristic?</font><br><br><font size="2">Graham Yiu<br>LLVM Compiler Development<br>IBM Toronto Software Lab<br>Office: (905) 413-4077 C2-707/8200/Markham<br>Email: gyiu@ca.ibm.com</font><br><br><img width="16" height="16" src="cid:1__=8FBB0B3DDFC8F7338f9e8a93df938690918c8FB@" border="0" alt="Inactive hide details for "Jun Lim" ---10/03/2017 12:21:38 PM---Hi Graham,"><font size="2" color="#424282">"Jun Lim" ---10/03/2017 12:21:38 PM---Hi Graham,</font><br><br><font size="2" color="#5F5F5F">From: </font><font size="2">"Jun Lim" <junbuml@codeaurora.org></font><br><font size="2" color="#5F5F5F">To: </font><font size="2">"'Graham Yiu'" <gyiu@ca.ibm.com></font><br><font size="2" color="#5F5F5F">Cc: </font><font size="2"><llvm-dev@lists.llvm.org></font><br><font size="2" color="#5F5F5F">Date: </font><font size="2">10/03/2017 12:21 PM</font><br><font size="2" color="#5F5F5F">Subject: </font><font size="2">RE: [llvm-dev] General question about enabling partial inlining</font><br><hr width="100%" size="2" align="left" noshade style="color:#8091A5; "><br><br><br><font face="Calibri">Hi Graham, </font><br><font face="Calibri"> </font><br><font face="Calibri">Thanks for sharing this. Are you planning on enabling the pass only on PGO? Even in non-PGO, I noticed some performance gains when we are aggressive in partially inlining the early return part, especially when the callee spill CSRs in the entry block. At a high level, I have two questions: </font><br><font size="2">1. </font><font face="Calibri">What is the main obstacle that prevent the pass from being enabled by default? </font><br><font size="2">2. </font><font face="Calibri">Would it make sense to give some bonus in the cost model when we detect the possibility of spilling CSRs in the entry block? </font><br><font face="Calibri"> </font><br><font face="Calibri">Thanks,</font><br><font face="Calibri">Jun</font><br><b><font face="Calibri">From:</font></b><font face="Calibri"> Graham Yiu [</font><font face="Calibri"><a href="mailto:gyiu@ca.ibm.com">mailto:gyiu@ca.ibm.com</a></font><font face="Calibri">] </font><b><font face="Calibri"><br>Sent:</font></b><font face="Calibri"> Tuesday, October 3, 2017 11:08 AM</font><b><font face="Calibri"><br>To:</font></b><font face="Calibri"> junbuml@codeaurora.org</font><b><font face="Calibri"><br>Cc:</font></b><font face="Calibri"> llvm-dev@lists.llvm.org</font><b><font face="Calibri"><br>Subject:</font></b><font face="Calibri"> Re: [llvm-dev] General question about enabling partial inlining</font><br><font face="Calibri"> </font><p><font size="2">Hi Jun,</font><br><font size="2"><br>We're actually looking at enhancing the partial inlining pass right now (see </font><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.llvm.org_pipermail_llvm-2Ddev_2017-2DAugust_116515.html&d=DwMFAg&c=jf_iaSHvJObTbx-siA1ZOg&r=4ST7e3kMd0GTi3w9ByK5Cw&m=9oYOvB3l33-euX7ag6texitDSABCTLWfauz0YGW7zZ8&s=lZOJDeoavpuEHo29CLd9Kvkn1ibSdgK5125f13O-LYQ&e="><u><font size="2" color="#0000FF">http://lists.llvm.org/pipermail/llvm-dev/2017-August/116515.html</font></u></a><font size="2">)</font><br><font size="2"><br>We'd be interested in turning on the pass by default some time in the future, if our enhancements prove beneficial.</font><br><font size="2"><br>Cheers,</font><br><font size="2"><br>Graham Yiu<br>LLVM Compiler Development<br>IBM Toronto Software Lab<br>Office: (905) 413-4077 C2-707/8200/Markham<br>Email: </font><a href="mailto:gyiu@ca.ibm.com"><u><font size="2" color="#0000FF">gyiu@ca.ibm.com</font></u></a><br><br><img src="cid:1__=8FBB0B3DDFC8F7338f9e8a93df938690918c8FB@" width="16" height="16" alt="Inactive hide details for via llvm-dev ---09/13/2017 01:12:02 PM---Hi, I noticed some performance gains in some spec benchmarks"><font size="2" color="#424282">via llvm-dev ---09/13/2017 01:12:02 PM---Hi, I noticed some performance gains in some spec benchmarks without</font><br><font size="2" color="#5F5F5F"><br>From: </font><font size="2">via llvm-dev <</font><a href="mailto:llvm-dev@lists.llvm.org"><u><font size="2" color="#0000FF">llvm-dev@lists.llvm.org</font></u></a><font size="2">></font><font size="2" color="#5F5F5F"><br>To: </font><a href="mailto:llvm-dev@lists.llvm.org"><u><font size="2" color="#0000FF">llvm-dev@lists.llvm.org</font></u></a><font size="2" color="#5F5F5F"><br>Date: </font><font size="2">09/13/2017 01:12 PM</font><font size="2" color="#5F5F5F"><br>Subject: </font><font size="2">[llvm-dev] General question about enabling partial inlining</font><font size="2" color="#5F5F5F"><br>Sent by: </font><font size="2">"llvm-dev" <</font><a href="mailto:llvm-dev-bounces@lists.llvm.org"><u><font size="2" color="#0000FF">llvm-dev-bounces@lists.llvm.org</font></u></a><font size="2">></font><br><hr width="100%" size="2" align="left" noshade><br><font face="Calibri"><br><br></font><font size="2" face="Courier New"><br>Hi,<br><br>I noticed some performance gains in some spec benchmarks without <br>significant code size bloat when aggressively performing partial <br>inlining, especially when the original callee spill CSRs in the entry <br>block. I guess the partial inlining is not enabled mainly due to the <br>code size. Is there any other issue which prevent the pass from being <br>enabled? Do we have any plan or any on-going works to enable partial <br>inlining ?<br>Thanks,<br>Jun<br><br>-- <br>Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm <br>Technologies, Inc.<br>Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a <br>Linux Foundation Collaborative Project.<br>_______________________________________________<br>LLVM Developers mailing list</font><u><font size="2" color="#0000FF" face="Courier New"><br></font></u><a href="mailto:llvm-dev@lists.llvm.org"><u><font size="2" color="#0000FF" face="Courier New">llvm-dev@lists.llvm.org</font></u></a><u><font size="2" color="#0000FF" face="Courier New"><br></font></u><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.llvm.org_cgi-2Dbin_mailman_listinfo_llvm-2Ddev&d=DwIGaQ&c=jf_iaSHvJObTbx-siA1ZOg&r=4ST7e3kMd0GTi3w9ByK5Cw&m=zEValqMYe9FvZqI-GQUgWPmVUgbEq8OBAjTrBjz9xhY&s=1h4Cw3vDlJBIknkn0Ts3R_e3PU64h_dyvEkyCdonAVo&e="><u><font size="2" color="#0000FF" face="Courier New">https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.llvm.org_cgi-2Dbin_mailman_listinfo_llvm-2Ddev&d=DwIGaQ&c=jf_iaSHvJObTbx-siA1ZOg&r=4ST7e3kMd0GTi3w9ByK5Cw&m=zEValqMYe9FvZqI-GQUgWPmVUgbEq8OBAjTrBjz9xhY&s=1h4Cw3vDlJBIknkn0Ts3R_e3PU64h_dyvEkyCdonAVo&e=</font></u></a><font size="2" face="Courier New"> <br></font><font face="Calibri"><br><br></font><br><br><BR>
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