<div dir="ltr"><div>Well, the message mentions it. It's the `vselect` node in the .td file (ISD::VSELECT). You've clearly legalized it or otherwise emitted it post-legalization. So you need something similar to this in your .td file (but for your big vector type):<br>```<br>let Predicates = [HasAVX2] in { <br> def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),<br> (v32i8 VR256:$src2))),<br> (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;<br>}<br>```<br><br></div>This particular example comes from lib/Target/X86/X86InstrSSE.td, but there are other examples from other back ends that may be more fitting.<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Sep 21, 2017 at 10:18 AM, hameeza ahmed via llvm-dev <span dir="ltr"><<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div>Hello,<br><br></div>I am getting this error. What instruction is required to be implemented?<br><div><div><br><br>LLVM ERROR: Cannot select: t22: v32i32 = vselect t724, t11, t16<br> t724: v32i32,ch = load<LD128[FixedStack1]> t723, FrameIndex:i64<1>, undef:i64<br> t659: i64 = FrameIndex<1><br> t10: i64 = undef<br> t11: v32i32,ch = load<LD128[%sunkaddr45](align=<wbr>4)(tbaa=<0x481f1e8>)> t0, t8, undef:i64<br> t8: i64 = add t7, Constant:i64<4><br> t7: i64 = add t2, t63<br> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg97<br> t1: i64 = Register %vreg97<br> t63: i64 = shl t4, Constant:i8<2><br> t4: i64,ch = CopyFromReg t0, Register:i64 %vreg11<br> t3: i64 = Register %vreg11<br> t1889: i8 = Constant<2><br> t5: i64 = Constant<4><br> t10: i64 = undef<br> t16: v32i32,ch = CopyFromReg t0, Register:v32i32 %vreg14<br> t15: v32i32 = Register %vreg14<br>In function: int_to_uchar<br><br></div><div><br></div></div></div>
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