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Thanks for response. I think it depends on how we implement
TargetLowering. As you know, if it is not easy to match ISD node
with native target instructions, we usually lower ISD nodes. The
CodeGen's split function checks custom lowering first and try to
split the EXTRACT_VECTOR_ELT node. At this moment, I am not sure how
the ISD node is split with custom lowering because we need to manage
the SpliVectors on DAGTypeLegalizer. I could scalarize all vector
type on IR level. Additionally, several existing targets are using
"MVT::i1" register class.<br>
<div class="moz-forward-container"> <br>
Thanks,<br>
JinGu Kang<br>
<br>
P.S. Edinburgh is also cloudy. :(<br>
<br>
<div class="moz-cite-prefix">On 18/09/17 13:01, Jon Chesterfield
wrote:<br>
</div>
<blockquote type="cite"
cite="mid:CAOUYtQDXMsOeCsMeyLFtT1ki1SSC=fY3jxUOMC-iMb=vKA_Y5g@mail.gmail.com">
<div dir="auto">
<div>Hey. Replying off list so I be brief.</div>
<div dir="auto"><br>
</div>
<div dir="auto">Lots of stuff breaks when adding unusual
register classes. If you actually have i1 registers then
adding it as a register class is necessary.</div>
<div dir="auto"><br>
</div>
<div dir="auto">If you don't, then I fear you're looking at
the first of several problems. The most severe will be in
the calling convention implementation but there's also
mundane things like legal i1 implies addition, division etc
will be assumed to exist and llvm won't expand them usefully
if they don't.</div>
<div dir="auto"><br>
</div>
<div dir="auto">Better not to add it in my experience.</div>
<div dir="auto"><br>
</div>
<div dir="auto">Cheers</div>
<div dir="auto"><br>
</div>
<div dir="auto">p.s. I hope all is well in sunny Edinburgh.
We're down in Bristol with another out of tree target.<br>
<div class="gmail_extra" dir="auto"><br>
<div class="gmail_quote">On 18 Sep 2017 11:39, "<a
href="mailto:jingu@codeplay.com"
moz-do-not-send="true">jingu@codeplay.com</a>" <<a
href="mailto:jingu@codeplay.com"
moz-do-not-send="true">jingu@codeplay.com</a>>
wrote:<br type="attribution">
<blockquote class="quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex">
<div text="#000000" bgcolor="#FFFFFF">
<p>um... In order to reproduce the issue, we need to
add 'i1' register class and avoid all vector
register class on TargetLowering class... I am
getting the issue on my custom target. I will try
to find the existing target to reproduce the
issuet but I am not sure whether the existing
targets can reproduce the issue or not...</p>
<p>Thanks,</p>
<p>JinGu Kang<br>
</p>
<div class="elided-text"> <br>
<div class="m_-3706172854692361779moz-cite-prefix">On
17/09/17 06:40, Demikhovsky, Elena wrote:<br>
</div>
<blockquote type="cite">
<div class="m_-3706172854692361779WordSection1">
<p class="MsoNormal"><a
name="m_-3706172854692361779__MailEndCompose"
moz-do-not-send="true"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Please
open a bugzilla ticket and attach your
testcase. It will allow us to debug and
fix the problem.</span></a></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Thanks</span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"> </span></p>
<div>
<p class="MsoNormal"
style="margin-left:36.0pt"> <span
style="font-family:"Calibri",sans-serif;color:#2f5496"><span>-<span
style="font:7.0pt "Times New
Roman""> </span></span></span><span
dir="LTR"></span><b><i><span
style="color:#2f5496"> Elena</span></i></b></p>
</div>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"> </span></p>
<div>
<div style="border:none;border-top:solid
#e1e1e1 1.0pt;padding:3.0pt 0cm 0cm 0cm">
<p class="MsoNormal"
style="margin-left:36.0pt"><a
name="m_-3706172854692361779______replyseparator"
moz-do-not-send="true"></a><b><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:windowtext">From:</span></b><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:windowtext">
JinGu [<a
class="m_-3706172854692361779moz-txt-link-freetext"
href="mailto:jingu@codeplay.com"
target="_blank"
moz-do-not-send="true">mailto:jingu@codeplay.com</a>]
<br>
<b>Sent:</b> Saturday, September 16,
2017 00:38<br>
<b>To:</b> Demikhovsky, Elena <a
class="m_-3706172854692361779moz-txt-link-rfc2396E"
href="mailto:elena.demikhovsky@intel.com" target="_blank"
moz-do-not-send="true"><elena.demikhovsky@intel.com></a>;
<a
class="m_-3706172854692361779moz-txt-link-abbreviated"
href="mailto:daniel_l_sanders@apple.com" target="_blank"
moz-do-not-send="true">daniel_l_sanders@apple.com</a>
<a
class="m_-3706172854692361779moz-txt-link-rfc2396E"
href="mailto:daniel_l_sanders@apple.com" target="_blank"
moz-do-not-send="true"><daniel_l_sanders@apple.com></a>;
Jon Chesterfield <a
class="m_-3706172854692361779moz-txt-link-rfc2396E"
href="mailto:jonathanchesterfield@gmail.com" target="_blank"
moz-do-not-send="true"><jonathanchesterfield@gmail.<wbr>com></a><br>
<b>Cc:</b> <a
class="m_-3706172854692361779moz-txt-link-abbreviated"
href="mailto:llvm-dev@lists.llvm.org" target="_blank"
moz-do-not-send="true">llvm-dev@lists.llvm.org</a><br>
<b>Subject:</b> Re: Question about
'DAGTypeLegalizer::SplitVecOp_<wbr>EXTRACT_VECTOR_ELT'</span></p>
</div>
</div>
<p class="MsoNormal"
style="margin-left:36.0pt"> </p>
<p style="margin-left:36.0pt"><span
style="font-size:10.0pt;font-family:"Arial",sans-serif">Hi
Elena,</span></p>
<p class="MsoNormal"
style="margin-left:36.0pt"><span
style="font-size:10.0pt;font-family:"Arial",sans-serif">Thanks
for your response.<br>
<br>
The store is ok but the extending load
generates assertion after the store
because MemVT is i8 and VT is i1 on
following line.</span> </p>
<div>
<p class="MsoNormal"
style="margin-right:0cm;margin-bottom:12.0pt;margin-left:36.0pt"><span
style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#222222"><br>
assert(MemVT.getScalarType().<wbr>bitsLT(VT.getScalarType())
&& "Should only be an extending
load, not truncating!")<br>
<br>
so I think we need to use non-extending
load for element size less than 8bit on
"DAGTypeLegalizer::SplitVecOp_<wbr>EXTRACT_VECTOR_ELT" like
this roughly.</span><span
style="font-family:"Arial",sans-serif;color:#222222"></span></p>
<div>
<p class="MsoNormal"
style="margin-left:36.0pt"><span
style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#222222">if
(N->getOperand(0).<wbr>getValueType().<wbr>getVectorElementType().<wbr>getSizeInBits()
< 8) {<br>
return
DAG.getLoad(N->getValueType(0)<wbr>,
dl, Store, StackPtr,
MachinePointerInfo());<br>
} else {<br>
return DAG.getExtLoad(ISD::EXTLOAD,
dl, N->getValueType(0), Store,
StackPtr, MachinePointerInfo()<wbr>,
EltVT);<br>
}</span><span
style="font-family:"Arial",sans-serif;color:#222222"></span></p>
</div>
<div>
<p class="MsoNormal"
style="margin-left:36.0pt"><span
style="font-family:"Arial",sans-serif;color:#222222"> </span></p>
</div>
<div>
<p class="MsoNormal"
style="margin-left:36.0pt"><span
style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#222222">How
do you think about it?</span><span
style="font-family:"Arial",sans-serif;color:#222222"></span></p>
</div>
<div>
<p class="MsoNormal"
style="margin-left:36.0pt"><span
style="font-family:"Arial",sans-serif;color:#222222"> </span></p>
</div>
<div>
<p class="MsoNormal"
style="margin-left:36.0pt"><span
style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#222222">Thanks,</span><span
style="font-family:"Arial",sans-serif;color:#222222"></span></p>
</div>
<div>
<p class="MsoNormal"
style="margin-left:36.0pt"><span
style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#222222">JinGu
Kang</span><span
style="font-family:"Arial",sans-serif;color:#222222"></span></p>
</div>
</div>
<p class="MsoNormal"
style="margin-left:36.0pt"> </p>
<div>
<p class="MsoNormal"
style="margin-left:36.0pt">On 15/09/2017
18:42, Demikhovsky, Elena wrote:</p>
</div>
<blockquote
style="margin-top:5.0pt;margin-bottom:5.0pt">
<blockquote
style="margin-top:5.0pt;margin-bottom:5.0pt">
<pre style="margin-left:36.0pt">extends the elements to 8bit and stores them on stack.</pre>
</blockquote>
<pre style="margin-left:36.0pt">Store is responsible for zero-extend. This is the policy...</pre>
<pre style="margin-left:36.0pt"> </pre>
<pre style="margin-left:36.0pt">- Elena</pre>
<pre style="margin-left:36.0pt"> </pre>
<pre style="margin-left:36.0pt"> </pre>
<pre style="margin-left:36.0pt">-----Original Message-----</pre>
<pre style="margin-left:36.0pt">From: <a href="mailto:jingu@codeplay.com" target="_blank" moz-do-not-send="true">jingu@codeplay.com</a> [<a href="mailto:jingu@codeplay.com" target="_blank" moz-do-not-send="true">mailto:jingu@codeplay.com</a>] </pre>
<pre style="margin-left:36.0pt">Sent: Friday, September 15, 2017 17:45</pre>
<pre style="margin-left:36.0pt">To: <a href="mailto:llvm-dev@lists.llvm.org" target="_blank" moz-do-not-send="true">llvm-dev@lists.llvm.org</a>; Demikhovsky, Elena <a href="mailto:elena.demikhovsky@intel.com" target="_blank" moz-do-not-send="true"><elena.demikhovsky@intel.com></a>; <a href="mailto:daniel_l_sanders@apple.com" target="_blank" moz-do-not-send="true">daniel_l_sanders@apple.com</a></pre>
<pre style="margin-left:36.0pt">Subject: Re: Question about 'DAGTypeLegalizer::SplitVecOp_<wbr>EXTRACT_VECTOR_ELT'</pre>
<pre style="margin-left:36.0pt"> </pre>
<pre style="margin-left:36.0pt">Can someone give the comment about it please?</pre>
<pre style="margin-left:36.0pt"> </pre>
<pre style="margin-left:36.0pt">Thanks,</pre>
<pre style="margin-left:36.0pt"> </pre>
<pre style="margin-left:36.0pt">JinGu Kang</pre>
<pre style="margin-left:36.0pt"> </pre>
<pre style="margin-left:36.0pt"> </pre>
<pre style="margin-left:36.0pt">On 14/09/17 12:05, <a href="mailto:jingu@codeplay.com" target="_blank" moz-do-not-send="true">jingu@codeplay.com</a> wrote:</pre>
<blockquote
style="margin-top:5.0pt;margin-bottom:5.0pt">
<pre style="margin-left:36.0pt">Hi All,</pre>
<pre style="margin-left:36.0pt"> </pre>
<pre style="margin-left:36.0pt">I have a question about splitting 'EXTRACT_VECTOR_ELT' with 'v2i1'. I </pre>
<pre style="margin-left:36.0pt">have a llvm IR code snippet as following:</pre>
<pre style="margin-left:36.0pt"> </pre>
<pre style="margin-left:36.0pt">llvm IR code snippet:</pre>
<pre style="margin-left:36.0pt"> </pre>
<pre style="margin-left:36.0pt">for.body: <wbr> ; preds = %entry, </pre>
<pre style="margin-left:36.0pt">%for.cond</pre>
<pre style="margin-left:36.0pt"> %i.022 = phi i32 [ 0, %entry ], [ %inc, %for.cond ]</pre>
<pre style="margin-left:36.0pt"> %0 = icmp ne <2 x i32> %vecinit1, <i32 0, i32 -23></pre>
<pre style="margin-left:36.0pt"> %1 = extractelement <2 x i1> %0, i32 %i.022</pre>
<pre style="margin-left:36.0pt"> %vecext4 = extractelement <2 x i32> %vecinit1, i32 %i.022</pre>
<pre style="margin-left:36.0pt"> %vecext5 = extractelement <2 x i32> <i32 0, i32 -23>, i32 %i.022</pre>
<pre style="margin-left:36.0pt"> %cmp6 = icmp ne i32 %vecext4, %vecext5</pre>
<pre style="margin-left:36.0pt"> %cmp7 = xor i1 %1, %cmp6</pre>
<pre style="margin-left:36.0pt"> </pre>
<pre style="margin-left:36.0pt">...</pre>
<pre style="margin-left:36.0pt"> </pre>
<pre style="margin-left:36.0pt">and the SelectionDAG before TypeLegalizer is like this.</pre>
<pre style="margin-left:36.0pt"> </pre>
<pre style="margin-left:36.0pt"> t0: ch = EntryToken</pre>
<pre style="margin-left:36.0pt"> t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0</pre>
<pre style="margin-left:36.0pt"> t3: ch = ValueType:i32</pre>
<pre style="margin-left:36.0pt"> t5: i32,ch = CopyFromReg t2:1, Register:i32 %vreg1</pre>
<pre style="margin-left:36.0pt"> t7: i32 = AssertZext t5, ValueType:ch:i1</pre>
<pre style="margin-left:36.0pt"> t8: v2i32 = BUILD_VECTOR t2, t7</pre>
<pre style="margin-left:36.0pt"> t11: v2i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<-23></pre>
<pre style="margin-left:36.0pt"> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2</pre>
<pre style="margin-left:36.0pt"> t22: i32 = add t15, Constant:i32<1></pre>
<pre style="margin-left:36.0pt"> t24: ch = CopyToReg t0, Register:i32 %vreg3, t22</pre>
<pre style="margin-left:36.0pt"> t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1></pre>
<pre style="margin-left:36.0pt"> t31: ch = TokenFactor t24, t27</pre>
<pre style="margin-left:36.0pt"> t13: v2i1 = setcc t8, t11, setne:ch</pre>
<pre style="margin-left:36.0pt"> t16: i1 = extract_vector_elt t13, t15</pre>
<pre style="margin-left:36.0pt"> t17: i32 = extract_vector_elt t8, t15</pre>
<pre style="margin-left:36.0pt"> t18: i32 = extract_vector_elt t11, t15</pre>
<pre style="margin-left:36.0pt"> t19: i1 = setcc t17, t18, setne:ch</pre>
<pre style="margin-left:36.0pt"> t20: i1 = xor t16, t19</pre>
<pre style="margin-left:36.0pt"> </pre>
<pre style="margin-left:36.0pt">...</pre>
<pre style="margin-left:36.0pt"> </pre>
<pre style="margin-left:36.0pt">I have not added any vector register class so 'DAGTypeLegalizer' tries </pre>
<pre style="margin-left:36.0pt">to split the "t16: i1 = extract_vector_elt t13, t15" because t13's </pre>
<pre style="margin-left:36.0pt">result type is 'v2i1'. If the size of vector element is less than </pre>
<pre style="margin-left:36.0pt">8bit, 'DAGTypeLegalizer::SplitVecOp_<wbr>EXTRACT_VECTOR_ELT()' function </pre>
<pre style="margin-left:36.0pt">extends the elements to 8bit and stores them on stack. Finally, the </pre>
<pre style="margin-left:36.0pt">function generates 'ExtLoad' to load specific element. But if the </pre>
<pre style="margin-left:36.0pt">element's size is less than 8bit, I think it could be wrong. It looks </pre>
<pre style="margin-left:36.0pt">it needs just 'Load' or "Load and Truncate" to match the result type </pre>
<pre style="margin-left:36.0pt">of 'EXTRACT_VECTOR_ELT'. How do you think about it? If I missed </pre>
<pre style="margin-left:36.0pt">something, please let me know.</pre>
<pre style="margin-left:36.0pt"> </pre>
<pre style="margin-left:36.0pt">Thanks,</pre>
<pre style="margin-left:36.0pt"> </pre>
<pre style="margin-left:36.0pt">JinGu Kang</pre>
<pre style="margin-left:36.0pt"> </pre>
</blockquote>
<pre style="margin-left:36.0pt"> </pre>
<pre style="margin-left:36.0pt">------------------------------<wbr>------------------------------<wbr>---------</pre>
<pre style="margin-left:36.0pt">Intel Israel (74) Limited</pre>
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<pre style="margin-left:36.0pt">This e-mail and any attachments may contain confidential material for</pre>
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