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<p>Hi All,<br>
<br>
Thank you all for your advices. (Especially Ruiling, your phi nodes hints solves pretty much all of my problems!)<br>
Currently,i am facing issue with the optimization.<br>
<br>
One of my redefined basic block is as below:<br>
<span style="font-family:"Calibri",sans-serif"><br>
#BB_2: sub $vreg3,$vreg3,1 <br>
sll $vreg2,$vreg2,1 <br>
j #BB_1 <br>
<br>
</span>The implementation works fine for O0 invocation. <br>
But for O1,O2,O3, the instruction is reordered.<br>
The j instruction is reordered to <span style="font-family:"Calibri",sans-serif">
execute before sll:<br>
<br>
#BB_2: sub $vreg3,$vreg3,1<br>
<span style="font-family:"Calibri",sans-serif"><span style="font-family:"Calibri",sans-serif"> j #BB_1</span></span><br>
<span style="font-family:"Calibri",sans-serif"> sll $vreg2,$vreg2,1 <br>
</span> <br>
I am guessing the optimization reordered sll in the jump delay slot, and the instruction in jump delay slot is assumed to be executed everytime?
<br>
Is there a way to force the j and sll to be in-order as shown in my previous basic block even with the optimization?
<br>
Or llc accepts parameters to turn off mips jump delay slot?<br>
<br>
Chuan. </span><br>
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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> Song, Ruiling <ruiling.song@intel.com><br>
<b>Sent:</b> Friday, September 15, 2017 9:25 AM<br>
<b>To:</b> qcolombet@apple.com; jin chuan see<br>
<b>Cc:</b> Matthias Braun; llvm-dev@lists.llvm.org<br>
<b>Subject:</b> RE: [llvm-dev] Live Register Spilling</font>
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<b><span style="font-size:11.0pt; font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt; font-family:"Calibri",sans-serif"> qcolombet@apple.com [mailto:qcolombet@apple.com]
<br>
<b>Sent:</b> Friday, September 15, 2017 1:32 AM<br>
<b>To:</b> jin chuan see <jinchuansee@hotmail.com><br>
<b>Cc:</b> Song, Ruiling <ruiling.song@intel.com>; Matthias Braun <mbraun@apple.com>; llvm-dev@lists.llvm.org<br>
<b>Subject:</b> Re: [llvm-dev] Live Register Spilling</span></p>
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On Sep 13, 2017, at 9:03 PM, jin chuan see via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" style="color: blue; text-decoration: underline;">llvm-dev@lists.llvm.org</a>> wrote:</p>
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<span style="font-family:"Calibri",sans-serif">Hi All,<br>
<br>
Thanks for the reply. I managed to identify and fixed a few errors in my implementation.<br>
<br>
However, there are a few errors that i am not sure what is it indicating.<br>
For starters, i think i should explain what i am trying to achieve.<br>
<br>
I am actually working on MIPS backend to generate smaller set of MIPS Instructions compared to its existing supported instructions.<br>
Currently, i am working on shifting instructions.<br>
<br>
Take an example:<br>
A typical mips sllv syntax goes in this manner:<br>
<br>
sllv $reg1,$reg2,$reg3<br>
<br>
The $reg3 contains the shifting amount. Only the LSB 5 bit will be used.<br>
The $reg2 contains the data to be shifted.<br>
The $reg1 contains the data after shifting is performed.<br>
<br>
What i want to achieve is to expand sllv instruction to the following routine:<br>
<br>
andi $reg3,$reg3,0x1f //To mask the 5 bit LSB shifting amount<span style=""> </span><br>
#BB_1: beq $reg3,$zero,#BB_2 //Branch out from basic block if shifting amount is zero<br>
sub $reg3,$reg3,1 //To subtract 1 from the shifting amount<br>
sll $reg2,$reg2,1 //Shift by 1 bit<br>
j #BB_1 //Branch back to the begining of the routine<br>
#BB_2: addu $reg1,$reg2,$zero //Transfer the completed shift data to the original destination register<br>
<br>
Since you guys mentioned that the MI are represented in MachineSSA form, i imagined my routine represented by virtual registers would look something like this:<br>
<br>
andi $vreg3,$vreg3,0x1f <br>
#BB_1: beq $vreg3,$zero,#BB_2 <br>
sub $vreg3,$vreg3,1 <br>
sll $vreg2,$vreg2,1 <br>
j #BB_1 <br>
#BB_2: addu $vreg1,$vreg2,$zero </span></p>
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Hi Chuan,</p>
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In your example, you should not try to define $vreg3 many times. In SSA form, each value should be defined only once.</p>
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You need to create some new virtual registers and make sure each virtual register will be defined only once.</p>
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In your example you may need PHI node. Which is an important concept in SSA. You may need to google it to teach yourself on this.</p>
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And you should not insert normal arithmetic instructions between two branch/jump instructions. In your example, there are sub/sll between beq/j. which is invalid.</p>
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A ‘basic block’ should only terminate(br/jump) at the last one or two instructions.</p>
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llc has many useful options besides verify instructions. It also support printing machine IR before/after each pass which is also very useful. Try ‘llc --help’</p>
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Ruiling</p>
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