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<p><font face="arial,sans-serif" size="-1">Hi Elena,</font></p>
<font face="arial,sans-serif" size="-1">Thanks for your response.<br>
<br>
The store is ok but the extending load generates assertion after
the store because MemVT is i8 and VT is i1 on following line.</font>
<div style="color: rgb(34, 34, 34); font-family: arial, sans-serif;
font-size: small; font-style: normal; font-variant-ligatures:
normal; font-variant-caps: normal; font-weight: normal;
letter-spacing: normal; orphans: 2; text-align: start;
text-indent: 0px; text-transform: none; white-space: normal;
widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px;
text-decoration-style: initial; text-decoration-color: initial;"><font
size="-1"><br>
assert(MemVT.getScalarType().bitsLT(VT.getScalarType())
&& "Should only be an extending load, not truncating!")<br>
<br>
so I think we need to use non-extending load for element size
less than 8bit on
"DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT" <span
class="sewq36ksgrnqs73"></span><span class="sewq36ksgrnqs73"></span>like
this roughly.<br>
<br>
</font>
<div><font size="-1">if
(N->getOperand(0).getValueType().getVectorElementType().getSizeInBits()
< 8) {<br>
return DAG.getLoad(N->getValueType(0), dl, Store,
StackPtr, MachinePointerInfo());<br>
} else {<br>
return DAG.getExtLoad(ISD::EXTLOAD, dl,
N->getValueType(0), Store, StackPtr, MachinePointerInfo(),
EltVT);<br>
}</font></div>
<div><font size="-1"><br>
</font></div>
<div><font size="-1">How do you think about it?</font></div>
<div><font size="-1"><br>
</font></div>
<div><font size="-1">Thanks,</font></div>
<div><font size="-1">JinGu Kang</font></div>
</div>
<br>
<div class="moz-cite-prefix">On 15/09/2017 18:42, Demikhovsky, Elena
wrote:<br>
</div>
<blockquote
cite="mid:A0DC88CEB3010344830D52D66533DA8E5EE2F88D@hasmsx108.ger.corp.intel.com"
type="cite">
<blockquote type="cite">
<pre wrap="">extends the elements to 8bit and stores them on stack.
</pre>
</blockquote>
<pre wrap="">Store is responsible for zero-extend. This is the policy...
- Elena
-----Original Message-----
From: <a class="moz-txt-link-abbreviated" href="mailto:jingu@codeplay.com">jingu@codeplay.com</a> [<a class="moz-txt-link-freetext" href="mailto:jingu@codeplay.com">mailto:jingu@codeplay.com</a>]
Sent: Friday, September 15, 2017 17:45
To: <a class="moz-txt-link-abbreviated" href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a>; Demikhovsky, Elena <a class="moz-txt-link-rfc2396E" href="mailto:elena.demikhovsky@intel.com"><elena.demikhovsky@intel.com></a>; <a class="moz-txt-link-abbreviated" href="mailto:daniel_l_sanders@apple.com">daniel_l_sanders@apple.com</a>
Subject: Re: Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
Can someone give the comment about it please?
Thanks,
JinGu Kang
On 14/09/17 12:05, <a class="moz-txt-link-abbreviated" href="mailto:jingu@codeplay.com">jingu@codeplay.com</a> wrote:
</pre>
<blockquote type="cite">
<pre wrap="">Hi All,
I have a question about splitting 'EXTRACT_VECTOR_ELT' with 'v2i1'. I
have a llvm IR code snippet as following:
llvm IR code snippet:
for.body: ; preds = %entry,
%for.cond
%i.022 = phi i32 [ 0, %entry ], [ %inc, %for.cond ]
%0 = icmp ne <2 x i32> %vecinit1, <i32 0, i32 -23>
%1 = extractelement <2 x i1> %0, i32 %i.022
%vecext4 = extractelement <2 x i32> %vecinit1, i32 %i.022
%vecext5 = extractelement <2 x i32> <i32 0, i32 -23>, i32 %i.022
%cmp6 = icmp ne i32 %vecext4, %vecext5
%cmp7 = xor i1 %1, %cmp6
...
and the SelectionDAG before TypeLegalizer is like this.
t0: ch = EntryToken
t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0
t3: ch = ValueType:i32
t5: i32,ch = CopyFromReg t2:1, Register:i32 %vreg1
t7: i32 = AssertZext t5, ValueType:ch:i1
t8: v2i32 = BUILD_VECTOR t2, t7
t11: v2i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<-23>
t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2
t22: i32 = add t15, Constant:i32<1>
t24: ch = CopyToReg t0, Register:i32 %vreg3, t22
t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1>
t31: ch = TokenFactor t24, t27
t13: v2i1 = setcc t8, t11, setne:ch
t16: i1 = extract_vector_elt t13, t15
t17: i32 = extract_vector_elt t8, t15
t18: i32 = extract_vector_elt t11, t15
t19: i1 = setcc t17, t18, setne:ch
t20: i1 = xor t16, t19
...
I have not added any vector register class so 'DAGTypeLegalizer' tries
to split the "t16: i1 = extract_vector_elt t13, t15" because t13's
result type is 'v2i1'. If the size of vector element is less than
8bit, 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT()' function
extends the elements to 8bit and stores them on stack. Finally, the
function generates 'ExtLoad' to load specific element. But if the
element's size is less than 8bit, I think it could be wrong. It looks
it needs just 'Load' or "Load and Truncate" to match the result type
of 'EXTRACT_VECTOR_ELT'. How do you think about it? If I missed
something, please let me know.
Thanks,
JinGu Kang
</pre>
</blockquote>
<pre wrap="">
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</pre>
</blockquote>
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