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<p class="MsoNormal">Hi,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I’m implementing the registers allocation for Instructions Set where arithmetic operations only have two input explicit operands.<o:p></o:p></p>
<p class="MsoNormal">The result is always assigned to an implicit output register depending of the operation.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">For example, the LADDS_A_oo operation has two inputs offset operands, but the output is FA_ROUTADD register.<o:p></o:p></p>
<p class="MsoNormal"><o:p></o:p></p>
<p class="MsoNormal" style="text-autospace:none"><span style="font-size:10.0pt;font-family:Monospace">
<u><span style="color:#1A1A1A">def</span></u> LADDS_A_oo : CLPFPU_A_oo<0b0000100001,<o:p></o:p></span></p>
<p class="MsoNormal" style="text-autospace:none"><span style="font-size:10.0pt;font-family:Monospace"> (ins FPUaOffsetOperand:$OffsetA,FPUaOffsetOperand:$OffsetB),<o:p></o:p></span></p>
<p class="MsoNormal" style="text-autospace:none"><span style="font-size:10.0pt;font-family:Monospace"> (outs FPUaROUTRegisterClass:$FA_ROUTADD),<o:p></o:p></span></p>
<p class="MsoNormal" style="text-autospace:none"><span style="font-size:10.0pt;font-family:Monospace"> [FA_ROUTADD,RFLAGA], // list of implicit registers<o:p></o:p></span></p>
<p class="MsoNormal" style="text-autospace:none"><span style="font-size:10.0pt;font-family:Monospace"> "ladds_a\t$OffsetA,$OffsetB",<o:p></o:p></span></p>
<p class="MsoNormal" style="text-autospace:none"><span style="font-size:10.0pt;font-family:Monospace"> [(set i16:$FA_ROUTADD, (add i16:$OffsetA, i16:$OffsetB))],NoItinerary>;<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">A small code seems to be correctly lowered as follow.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Total amount of phi nodes to update: 0<o:p></o:p></p>
<p class="MsoNormal">*** MachineFunction at end of ISel ***<o:p></o:p></p>
<p class="MsoNormal"># Machine code for function add16_reg_reg: SSA<o:p></o:p></p>
<p class="MsoNormal">Function Live Ins: %FA_ROFF0 in %vreg0, %FA_ROFF1 in %vreg1<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">BB#0: derived from LLVM BB %0<o:p></o:p></p>
<p class="MsoNormal"> Live Ins: %FA_ROFF0 %FA_ROFF1<o:p></o:p></p>
<p class="MsoNormal"> %vreg1<def> = COPY %FA_ROFF1; FPUaOffsetClass:%vreg1<o:p></o:p></p>
<p class="MsoNormal"> %vreg0<def> = COPY %FA_ROFF0; FPUaOffsetClass:%vreg0<o:p></o:p></p>
<p class="MsoNormal"> %vreg2<def> = LADDS_A_oo %vreg0, %vreg1, %FA_ROUTADD<imp-def,dead>, %RFLAGA<imp-def,dead>; FPUaROUTRegisterClass:%vreg2 FPUaOffsetClass:%vreg0,%vreg1<o:p></o:p></p>
<p class="MsoNormal"> %FA_ROFF0<def> = COPY %vreg2; FPUaROUTRegisterClass:%vreg2<o:p></o:p></p>
<p class="MsoNormal"> %vreg3<def> = MOVSUTO_SU_os_rpc 0, %FA_ROFF0<imp-use>; SUSpecialRPCRegisterClass:%vreg3<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"># End machine code for function add16_reg_reg.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal" style="margin-bottom:12.0pt">From a register allocation point of view, this program will work only if vreg2 is allocated to the FA_ROUTADD register.<o:p></o:p></p>
<p class="MsoNormal" style="margin-bottom:12.0pt">Is there a registers allocation pass that substitute the virtual register (vreg2) allocated to be assigned to the result of the operation with the physical one (FA_ROUTADD) where the result is assigned by the
processor?<o:p></o:p></p>
<p class="MsoNormal" style="margin-bottom:12.0pt">The physical register depend of the operations for additions it is FA_ROUTADD, but for division it is FA_ROUTDIV and multiplication it is FA_ROUTMUL?<o:p></o:p></p>
<p class="MsoNormal" style="margin-bottom:12.0pt">Thanks, Dominique Torette.
<span style="font-size:12.0pt;font-family:"Times New Roman","serif""><br>
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<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Times New Roman","serif""><img width="536" height="49" id="_x0000_i1025" src="http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg" alt="http://www.spacebel.be/wp-content/uploads/2011/06/image-sign-sbp.jpg"></span><span style="font-size:12.0pt;font-family:"Times New Roman","serif""><o:p></o:p></span></p>
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<p class="MsoNormal" align="center" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;text-align:center">
<b><span style="font-size:10.0pt">Dominique Torette</span></b><span style="font-size:10.0pt">
<br>
System Architect<br>
Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur <br>
Tel: +32 (0) 4 361 81 </span><span lang="FR-BE" style="font-size:10.0pt">11 - Fax: +32 (0) 4 361 81 20
<br>
</span><span style="font-size:10.0pt"><a href="http://www.spacebel.be/"><span lang="FR-BE" style="color:blue">www.spacebel.be</span></a></span><span lang="FR-BE" style="font-size:12.0pt;font-family:"Times New Roman","serif""><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="FR-BE"><o:p> </o:p></span></p>
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