<div dir="ltr"><span style="font-size:12.8px">Hello,</span><div style="font-size:12.8px"><br></div><div style="font-size:12.8px">I have defined 8 registers in <a href="http://registerinfo.td/" target="_blank">registerinfo.td</a> file in the following order:</div><div style="font-size:12.8px">R_0, R_1, R_2, R_3, R_4, R_5, R_6, R_7</div><div style="font-size:12.8px"><br></div><div style="font-size:12.8px">But the generated assembly code only uses 2 registers. How to enable it to use all 8? Also can i control the ordering like after R_0 can i use R_5 without changes in <a href="http://registerinfo.td/" target="_blank">registerinfo.td</a>?</div><div style="font-size:12.8px"><br></div><div style="font-size:12.8px">What changes are required here? either in scheduling or register allocation phases?<br><div><br></div><div><br></div><div><br></div><div><div><span style="white-space:pre-wrap"> </span>P_2048B_LOAD_DWORD<span style="white-space:pre-wrap"> </span>R_0, Pword ptr [rip + b]</div><div><span style="white-space:pre-wrap"> </span>P_2048B_LOAD_DWORD<span style="white-space:pre-wrap"> </span>R_1, Pword ptr [rip + c]</div><div><span style="white-space:pre-wrap"> </span>P_2048B_VADD<span style="white-space:pre-wrap"> </span>R_0, R_1, R_0</div><div><span style="white-space:pre-wrap"> </span>P_2048B_STORE_DWORD<span style="white-space:pre-wrap"> </span>Pword ptr [rip + a], R_0</div><div><span style="white-space:pre-wrap"> </span>P_2048B_LOAD_DWORD<span style="white-space:pre-wrap"> </span>R_0, Pword ptr [rip + b+2048]</div><div><span style="white-space:pre-wrap"> </span>P_2048B_LOAD_DWORD<span style="white-space:pre-wrap"> </span>R_1, Pword ptr [rip + c+2048]</div><div><span style="white-space:pre-wrap"> </span>P_2048B_VADD<span style="white-space:pre-wrap"> </span>R_0, R_1, R_0</div><div><span style="white-space:pre-wrap"> </span>P_2048B_STORE_DWORD<span style="white-space:pre-wrap"> </span>Pword ptr [rip + a+2048], R_0</div><div><span style="white-space:pre-wrap"> </span>P_2048B_LOAD_DWORD<span style="white-space:pre-wrap"> </span>R_0, Pword ptr [rip + b+4096]</div><div><span style="white-space:pre-wrap"> </span>P_2048B_LOAD_DWORD<span style="white-space:pre-wrap"> </span>R_1, Pword ptr [rip + c+4096]</div><div><span style="white-space:pre-wrap"> </span>P_2048B_VADD<span style="white-space:pre-wrap"> </span>R_0, R_1, R_0</div><div><span style="white-space:pre-wrap"> </span>P_2048B_STORE_DWORD<span style="white-space:pre-wrap"> </span>Pword ptr [rip + a+4096], R_0</div><div><span style="white-space:pre-wrap"> </span>P_2048B_LOAD_DWORD<span style="white-space:pre-wrap"> </span>R_0, Pword ptr [rip + b+6144]</div><div><span style="white-space:pre-wrap"> </span>P_2048B_LOAD_DWORD<span style="white-space:pre-wrap"> </span>R_1, Pword ptr [rip + c+6144]</div><div><span style="white-space:pre-wrap"> </span>P_2048B_VADD<span style="white-space:pre-wrap"> </span>R_0, R_1, R_0</div><div><span style="white-space:pre-wrap"> </span>P_2048B_STORE_DWORD<span style="white-space:pre-wrap"> </span>Pword ptr [rip + a+6144], R_0</div></div></div><div style="font-size:12.8px"><br></div><div style="font-size:12.8px">Please help. I am stuck here.</div><div style="font-size:12.8px"><br></div><div style="font-size:12.8px">Thank You</div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Jun 26, 2017 at 2:12 PM, hameeza ahmed <span dir="ltr"><<a href="mailto:hahmed2305@gmail.com" target="_blank">hahmed2305@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr">Thank You</div><div class="gmail-HOEnZb"><div class="gmail-h5"><div class="gmail_extra"><br><div class="gmail_quote">On Sun, Jun 25, 2017 at 7:23 PM, Hal Finkel <span dir="ltr"><<a href="mailto:hfinkel@anl.gov" target="_blank">hfinkel@anl.gov</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div bgcolor="#FFFFFF"><p>Hi, Zvi,</p><p>I agree. In the context of targeting the KNL, however, I'm a bit concerned about the addressing, and specifically, the size of the resulting encoding:</p><p></p><blockquote type="cite"><div><p class="MsoNormal"><span style="color:red"> vmovdqu32 zmm0, zmmword ptr [rax + c+401280] ;load b[401280] in zmm0</span><u></u><u></u></p></div><span style="color:blue"> vpaddd zmm1, zmm1, zmmword ptr [rax + b+401344] ; zmm1<-zmm1+b[401344]</span></blockquote><p></p><p>The KNL can only deliver 16 bytes per cycle from the icache to the decoder. Essentially all of the instructions in the loop, as we seem to generate it, have 10-byte encodings:</p><p> 10: 62 f1 7e 48 6f 80 00 vmovdqu32 0x0(%rax),%zmm0<br> 17: 00 00 00 <br> 16: R_X86_64_32S c+0x61f00<br></p><p>...<br></p> 38: 62 f1 7d 48 fe 80 00 vpaddd 0x0(%rax),%zmm0,%zmm0<br> 3f: 00 00 00 <br> 3e: R_X86_64_32S b+0x61f00<br>...<br><br>and since this seems like a generic feature of how we generate code, it seems like we can end up decoder limited (it might even be decoder limited for this loop). We might want to less aggressive in generating complex addressing modes for the KNL. It seems like it would be better to materialize the base array addresses into a register to make the encodings shorter.<span class="gmail-m_8400329596548417011HOEnZb"><font color="#888888"><br><br> -Hal</font></span><div><div class="gmail-m_8400329596548417011h5"><br><br><div class="gmail-m_8400329596548417011m_76471207977597099moz-cite-prefix">On 06/25/2017 07:14 AM, Rackover, Zvi wrote:<br></div><blockquote type="cite"><div class="gmail-m_8400329596548417011m_76471207977597099WordSection1"><p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)">Hi Ahmed,<u></u><u></u></span></p><p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)"><u></u> <u></u></span></p><p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)">From what can be seen in the code snippet you provided, the reuse of XMM0 and XMM1 across loop-unroll instances does not inhibit instruction-level parallelism.<u></u><u></u></span></p><p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)">Modern X86 processors use register renaming that can eliminate the dependencies in the instruction stream. In the example you provided, the processor should be able to identify the 2-vloads + vadd + vstore sequences as independent and pipeline their execution.<u></u><u></u></span></p><p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)"><u></u> <u></u></span></p><p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)">Thanks, Zvi<u></u><u></u></span></p><p class="MsoNormal"><a name="m_8400329596548417011_m_76471207977597099__MailEndCompose"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)"><u></u> <u></u></span></a></p><div><div style="border-right:none;border-bottom:none;border-left:none;border-top:1pt solid rgb(225,225,225);padding:3pt 0cm 0cm"><p class="MsoNormal"><a name="m_8400329596548417011_m_76471207977597099______replyseparator"></a><b><span style="font-size:11pt;font-family:Calibri,sans-serif;color:windowtext">From:</span></b><span style="font-size:11pt;font-family:Calibri,sans-serif;color:windowtext"> Hal Finkel [<a class="gmail-m_8400329596548417011m_76471207977597099moz-txt-link-freetext" href="mailto:hfinkel@anl.gov" target="_blank">mailto:hfinkel@anl.gov</a>] <br><b>Sent:</b> Saturday, June 24, 2017 05:17<br><b>To:</b> hameeza ahmed <a class="gmail-m_8400329596548417011m_76471207977597099moz-txt-link-rfc2396E" href="mailto:hahmed2305@gmail.com" target="_blank"><hahmed2305@gmail.com></a>; <a class="gmail-m_8400329596548417011m_76471207977597099moz-txt-link-abbreviated" href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a><br><b>Cc:</b> Demikhovsky, Elena <a class="gmail-m_8400329596548417011m_76471207977597099moz-txt-link-rfc2396E" href="mailto:elena.demikhovsky@intel.com" target="_blank"><elena.demikhovsky@intel.com></a>; Rackover, Zvi <a class="gmail-m_8400329596548417011m_76471207977597099moz-txt-link-rfc2396E" href="mailto:zvi.rackover@intel.com" target="_blank"><zvi.rackover@intel.com></a>; Breger, Igor<a class="gmail-m_8400329596548417011m_76471207977597099moz-txt-link-rfc2396E" href="mailto:igor.breger@intel.com" target="_blank"><igor.breger@intel.com></a>; <a class="gmail-m_8400329596548417011m_76471207977597099moz-txt-link-abbreviated" href="mailto:craig.topper@gmail.com" target="_blank">craig.topper@gmail.com</a><br><b>Subject:</b> Re: [llvm-dev] AVX Scheduling and Parallelism<u></u><u></u></span></p></div></div><p class="MsoNormal"><u></u> <u></u></p><p>It is possible that the issue with scheduling is constrained due to pointer-aliasing assumptions. Could you share the source for the loop in question?<u></u><u></u></p><p>RIP-relative indexing, as I recall, is a feature of position-independent code. Based on what's below, it might cause problems by making the instruction encodings large. cc'ing some Intel folks for further comments.<u></u><u></u></p><p> -Hal<u></u><u></u></p><div><p class="MsoNormal">On 06/23/2017 09:02 PM, hameeza ahmed via llvm-dev wrote:<u></u><u></u></p></div><blockquote style="margin-top:5pt;margin-bottom:5pt"><div><p class="MsoNormal">Hello,<u></u><u></u></p><div><p class="MsoNormal"><u></u> <u></u></p></div><div><p class="MsoNormal">After generating AVX code for large no of iterations i came to realize that it still uses only 2 registers zmm0 and zmm1 when the loop urnroll factor=1024,<u></u><u></u></p></div><div><p class="MsoNormal"><u></u> <u></u></p></div><div><p class="MsoNormal">i wonder if this register allocation allows operations in parallel?<u></u><u></u></p></div><div><p class="MsoNormal"><u></u> <u></u></p></div><div><p class="MsoNormal">Also i know all the elements within a single vector instruction are computed in parallel but does the elements of multiple instructions computed in parallel? like are 2 vmov with different registers executed in parallel? it can be because each core has an AVX unit. does compiler exploit it?<u></u><u></u></p></div><div><p class="MsoNormal"><u></u> <u></u></p></div><div><p class="MsoNormal"><u></u> <u></u></p></div><div><p class="MsoNormal">secondly i am generating assembly for intel and there are some offset like rip register or some constant addition in memory index. why is that so?<u></u><u></u></p></div><div><p class="MsoNormal">eg.1<u></u><u></u></p></div><div><p class="MsoNormal"><u></u> <u></u></p></div><div><div><p class="MsoNormal"> vmovdqu32 zmm0, zmmword ptr [rip + c]<u></u><u></u></p></div><div><p class="MsoNormal"> vpaddd zmm0, zmm0, zmmword ptr [rip + b]<u></u><u></u></p></div><div><p class="MsoNormal"> vmovdqu32 zmmword ptr [rip + a], zmm0<u></u><u></u></p></div><div><p class="MsoNormal"> vmovdqu32 zmm0, zmmword ptr [rip + c+64]<u></u><u></u></p></div><div><p class="MsoNormal"> vpaddd zmm0, zmm0, zmmword ptr [rip + b+64]<u></u><u></u></p></div></div><div><p class="MsoNormal"><u></u> <u></u></p></div><div><p class="MsoNormal"><u></u> <u></u></p></div><div><p class="MsoNormal">and <u></u><u></u></p></div><div><p class="MsoNormal"><u></u> <u></u></p></div><div><p class="MsoNormal">eg. 2<u></u><u></u></p></div><div><p class="MsoNormal"><u></u> <u></u></p></div><div><div><p class="MsoNormal">mov rax, -393216<u></u><u></u></p></div><div><p class="MsoNormal"> .p2align 4, 0x90<u></u><u></u></p></div><div><p class="MsoNormal">.LBB0_1: # %vector.body<u></u><u></u></p></div><div><p class="MsoNormal"> # =>This Inner Loop Header: Depth=1<u></u><u></u></p></div><div><p class="MsoNormal"> <span style="color:blue">vmovdqu32 zmm1, zmmword ptr [rax + c+401344] ; load c[401344] in zmm1</span><u></u><u></u></p></div><div><p class="MsoNormal"><span style="color:red"> vmovdqu32 zmm0, zmmword ptr [rax + c+401280] ;load b[401280] in zmm0</span><u></u><u></u></p></div><div><p class="MsoNormal"><span style="color:blue"> vpaddd zmm1, zmm1, zmmword ptr [rax + b+401344] ; zmm1<-zmm1+b[401344]</span><u></u><u></u></p></div><div><p class="MsoNormal"><span style="color:blue"> vmovdqu32 zmmword ptr [rax + a+401344], zmm1 ; store zmm1 in c[401344]</span><u></u><u></u></p></div></div><div><div><p class="MsoNormal"> vmovdqu32 zmm1, zmmword ptr [rax + c+401216]<u></u><u></u></p></div><div><p class="MsoNormal"><span style="color:red"> vpaddd zmm0, zmm0, zmmword ptr [rax + b+401280] ; zmm0<-zmm0+b[401280]</span><u></u><u></u></p></div><div><p class="MsoNormal"><span style="color:red"> vmovdqu32 zmmword ptr [rax + a+401280], zmm0 ; store zmm0 in c[401280]</span><u></u><u></u></p></div><div><p class="MsoNormal"> vmovdqu32 zmm0, zmmword ptr [rax + c+401152]<u></u><u></u></p></div></div><div><p class="MsoNormal">........ in the remaining instructions also there is only zmm0 and zmm1 used?<u></u><u></u></p></div><div><p class="MsoNormal"><u></u> <u></u></p></div><div><p class="MsoNormal">As you can see in the above examples there could be multiple registers use. also i doubt if the above set of repeating instructions in eg. 2 are executed in parallel? and why repeat zmm0 and zmm1 cant it be more zmms and all in parallel, mean the one w/o dependency. for eg in above example blue has dependency in between and red has dependency among each other they cant be executed in parallel but blue and red can be executed in parallel?<u></u><u></u></p></div><div><p class="MsoNormal"><u></u> <u></u></p></div><div><p class="MsoNormal"><u></u> <u></u></p></div><div><p class="MsoNormal"><u></u> <u></u></p></div><div><p class="MsoNormal">Please correct me if I am wrong.<u></u><u></u></p></div><div><p class="MsoNormal"><u></u> <u></u></p></div><div><p class="MsoNormal"><u></u> <u></u></p></div></div><p class="MsoNormal"><br><br><br><u></u><u></u></p><pre>______________________________<wbr>_________________<u></u><u></u></pre><pre>LLVM Developers mailing list<u></u><u></u></pre><pre><a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a><u></u><u></u></pre><pre><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev" target="_blank">http://lists.llvm.org/cgi-bin/<wbr>mailman/listinfo/llvm-dev</a><u></u><u></u></pre></blockquote><p class="MsoNormal"><br><br><u></u><u></u></p><pre>-- <u></u><u></u></pre><pre>Hal Finkel<u></u><u></u></pre><pre>Lead, Compiler Technology and Programming Languages<u></u><u></u></pre><pre>Leadership Computing Facility<u></u><u></u></pre><pre>Argonne National Laboratory<u></u><u></u></pre></div><p>------------------------------<wbr>------------------------------<wbr>---------<br>Intel Israel (74) Limited</p><p>This e-mail and any attachments may contain confidential material for<br>the sole use of the intended recipient(s). Any review or distribution<br>by others is strictly prohibited. If you are not the intended<br>recipient, please contact the sender and delete all copies.</p></blockquote><br><pre class="gmail-m_8400329596548417011m_76471207977597099moz-signature" cols="72">--
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory</pre></div></div></div></blockquote></div><br></div></div></div></blockquote></div></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Sun, Jun 25, 2017 at 7:23 PM, Hal Finkel <span dir="ltr"><<a href="mailto:hfinkel@anl.gov" target="_blank">hfinkel@anl.gov</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div bgcolor="#FFFFFF" text="#000000">
<p>Hi, Zvi,</p>
<p>I agree. In the context of targeting the KNL, however, I'm a bit
concerned about the addressing, and specifically, the size of the
resulting encoding:</p><span class="">
<p>
</p><blockquote type="cite">
<div>
<p class="MsoNormal"><span style="color:red">
vmovdqu32 zmm0, zmmword ptr [rax + c+401280]
;load b[401280] in zmm0</span><u></u><u></u></p>
</div>
<span style="color:blue"> vpaddd zmm1,
zmm1, zmmword ptr [rax + b+401344] ;
zmm1<-zmm1+b[401344]</span></blockquote>
<p></p>
</span><p>The KNL can only deliver 16 bytes per cycle from the icache to
the decoder. Essentially all of the instructions in the loop, as
we seem to generate it, have 10-byte encodings:</p>
<p> 10: 62 f1 7e 48 6f 80 00 vmovdqu32 0x0(%rax),%zmm0<br>
17: 00 00 00 <br>
16: R_X86_64_32S c+0x61f00<br>
</p>
<p>...<br>
</p>
38: 62 f1 7d 48 fe 80 00 vpaddd 0x0(%rax),%zmm0,%zmm0<br>
3f: 00 00 00 <br>
3e: R_X86_64_32S b+0x61f00<br>
...<br>
<br>
and since this seems like a generic feature of how we generate code,
it seems like we can end up decoder limited (it might even be
decoder limited for this loop). We might want to less aggressive in
generating complex addressing modes for the KNL. It seems like it
would be better to materialize the base array addresses into a
register to make the encodings shorter.<span class="HOEnZb"><font color="#888888"><br>
<br>
-Hal</font></span><div><div class="h5"><br>
<br>
<div class="m_2915570016021842916moz-cite-prefix">On 06/25/2017 07:14 AM, Rackover, Zvi
wrote:<br>
</div>
<blockquote type="cite">
<div class="m_2915570016021842916WordSection1">
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Hi
Ahmed,<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">From
what can be seen in the code snippet you provided, the reuse
of XMM0 and XMM1 across loop-unroll instances does not
inhibit instruction-level parallelism.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Modern
X86 processors use register renaming that can eliminate the
dependencies in the instruction stream. In the example you
provided, the processor should be able to identify the
2-vloads + vadd + vstore sequences as independent and
pipeline their execution.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Thanks,
Zvi<u></u><u></u></span></p>
<p class="MsoNormal"><a name="m_2915570016021842916__MailEndCompose"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></a></p>
<div>
<div style="border:none;border-top:solid #e1e1e1 1.0pt;padding:3.0pt 0cm 0cm 0cm">
<p class="MsoNormal"><a name="m_2915570016021842916______replyseparator"></a><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:windowtext">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:windowtext">
Hal Finkel [<a class="m_2915570016021842916moz-txt-link-freetext" href="mailto:hfinkel@anl.gov" target="_blank">mailto:hfinkel@anl.gov</a>]
<br>
<b>Sent:</b> Saturday, June 24, 2017 05:17<br>
<b>To:</b> hameeza ahmed <a class="m_2915570016021842916moz-txt-link-rfc2396E" href="mailto:hahmed2305@gmail.com" target="_blank"><hahmed2305@gmail.com></a>;
<a class="m_2915570016021842916moz-txt-link-abbreviated" href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a><br>
<b>Cc:</b> Demikhovsky, Elena
<a class="m_2915570016021842916moz-txt-link-rfc2396E" href="mailto:elena.demikhovsky@intel.com" target="_blank"><elena.demikhovsky@intel.com></a>; Rackover, Zvi
<a class="m_2915570016021842916moz-txt-link-rfc2396E" href="mailto:zvi.rackover@intel.com" target="_blank"><zvi.rackover@intel.com></a>; Breger, Igor
<a class="m_2915570016021842916moz-txt-link-rfc2396E" href="mailto:igor.breger@intel.com" target="_blank"><igor.breger@intel.com></a>; <a class="m_2915570016021842916moz-txt-link-abbreviated" href="mailto:craig.topper@gmail.com" target="_blank">craig.topper@gmail.com</a><br>
<b>Subject:</b> Re: [llvm-dev] AVX Scheduling and
Parallelism<u></u><u></u></span></p>
</div>
</div>
<p class="MsoNormal"><u></u> <u></u></p>
<p>It is possible that the issue with scheduling is constrained
due to pointer-aliasing assumptions. Could you share the
source for the loop in question?<u></u><u></u></p>
<p>RIP-relative indexing, as I recall, is a feature of
position-independent code. Based on what's below, it might
cause problems by making the instruction encodings large.
cc'ing some Intel folks for further comments.<u></u><u></u></p>
<p> -Hal<u></u><u></u></p>
<div>
<p class="MsoNormal">On 06/23/2017 09:02 PM, hameeza ahmed via
llvm-dev wrote:<u></u><u></u></p>
</div>
<blockquote style="margin-top:5.0pt;margin-bottom:5.0pt">
<div>
<p class="MsoNormal">Hello, <u></u><u></u></p>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal">After generating AVX code for large
no of iterations i came to realize that it still uses
only 2 registers zmm0 and zmm1 when the loop urnroll
factor=1024,<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal">i wonder if this register allocation
allows operations in parallel?<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal">Also i know all the elements within a
single vector instruction are computed in parallel but
does the elements of multiple instructions computed in
parallel? like are 2 vmov with different registers
executed in parallel? it can be because each core has an
AVX unit. does compiler exploit it?<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal">secondly i am generating assembly for
intel and there are some offset like rip register or
some constant addition in memory index. why is that so?<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal">eg.1<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<div>
<p class="MsoNormal"> vmovdqu32 zmm0,
zmmword ptr [rip + c]<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"> vpaddd zmm0,
zmm0, zmmword ptr [rip + b]<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"> vmovdqu32 zmmword
ptr [rip + a], zmm0<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"> vmovdqu32 zmm0,
zmmword ptr [rip + c+64]<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"> vpaddd zmm0,
zmm0, zmmword ptr [rip + b+64]<u></u><u></u></p>
</div>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal">and <u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal">eg. 2<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<div>
<p class="MsoNormal">mov rax, -393216<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"> .p2align 4,
0x90<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal">.LBB0_1:
# %vector.body<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal">
# =>This Inner Loop Header: Depth=1<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"> <span style="color:blue">vmovdqu32 zmm1, zmmword ptr
[rax + c+401344] ; load c[401344] in
zmm1</span><u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><span style="color:red">
vmovdqu32 zmm0, zmmword ptr [rax + c+401280]
;load b[401280] in zmm0</span><u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><span style="color:blue">
vpaddd zmm1, zmm1, zmmword ptr [rax +
b+401344] ; zmm1<-zmm1+b[401344]</span><u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><span style="color:blue">
vmovdqu32 zmmword ptr [rax + a+401344], zmm1
; store zmm1 in c[401344]</span><u></u><u></u></p>
</div>
</div>
<div>
<div>
<p class="MsoNormal"> vmovdqu32 zmm1,
zmmword ptr [rax + c+401216]<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><span style="color:red">
vpaddd zmm0, zmm0, zmmword ptr [rax +
b+401280] ; zmm0<-zmm0+b[401280]</span><u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><span style="color:red">
vmovdqu32 zmmword ptr [rax + a+401280], zmm0
; store zmm0 in c[401280]</span><u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"> vmovdqu32 zmm0,
zmmword ptr [rax + c+401152]<u></u><u></u></p>
</div>
</div>
<div>
<p class="MsoNormal">........ in the remaining
instructions also there is only zmm0 and zmm1 used?<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal">As you can see in the above examples
there could be multiple registers use. also i doubt if
the above set of repeating instructions in eg. 2 are
executed in parallel? and why repeat zmm0 and zmm1 cant
it be more zmms and all in parallel, mean the one w/o
dependency. for eg in above example blue has dependency
in between and red has dependency among each other they
cant be executed in parallel but blue and red can be
executed in parallel?<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal">Please correct me if I am wrong.<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
</div>
<p class="MsoNormal"><br>
<br>
<br>
<u></u><u></u></p>
<pre>______________________________<wbr>_________________<u></u><u></u></pre>
<pre>LLVM Developers mailing list<u></u><u></u></pre>
<pre><a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a><u></u><u></u></pre>
<pre><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev" target="_blank">http://lists.llvm.org/cgi-bin/<wbr>mailman/listinfo/llvm-dev</a><u></u><u></u></pre>
</blockquote>
<p class="MsoNormal"><br>
<br>
<u></u><u></u></p>
<pre>-- <u></u><u></u></pre>
<pre>Hal Finkel<u></u><u></u></pre>
<pre>Lead, Compiler Technology and Programming Languages<u></u><u></u></pre>
<pre>Leadership Computing Facility<u></u><u></u></pre>
<pre>Argonne National Laboratory<u></u><u></u></pre>
</div>
<p>------------------------------<wbr>------------------------------<wbr>---------<br>
Intel Israel (74) Limited</p>
<p>This e-mail and any attachments may contain confidential
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</blockquote>
<br>
<pre class="m_2915570016021842916moz-signature" cols="72">--
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory</pre>
</div></div></div>
</blockquote></div><br></div>