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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link="#0563C1" vlink="#954F72"><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>Hi Wei Wei,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>You’re correct. The addLoopCarriedDependences function is creating loop carried store->load dependences only. The other dependences you’ve listed need to be added as well for correctness. The missing dependences are just an oversight.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>Thanks,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>Brendon<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'><o:p> </o:p></span></p><p class=MsoNormal><b><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>From:</span></b><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'> wei wei [mailto:wweiandrew@gmail.com] <br><b>Sent:</b> Thursday, August 17, 2017 10:50 AM<br><b>To:</b> bcahoon@codeaurora.org<br><b>Cc:</b> llvm-dev@lists.llvm.org<br><b>Subject:</b> Missing some cross iteration memory dependencies for software pipeline?<o:p></o:p></span></p><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal>Hi, bcahoon,<o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>I found in Machinepipeliner, addLoopCarriedDependences function only create store-->load true mem dependence when identifying recurrences.<o:p></o:p></p></div><div><p class=MsoNormal>But in ScheduleDAGInstrs, there may be three kinds of mem order dependencies(store-->load, load-->store, store-->store) inside one iteration.<o:p></o:p></p></div><div><p class=MsoNormal>When calculating loop carried dependence, in addition to register dependence(phis), we also need to consider the above three kinds of memory dependencies to build cross iterations graph.<o:p></o:p></p></div><div><p class=MsoNormal>For example,<o:p></o:p></p></div><div><p class=MsoNormal> STORE Reg1, Reg0 + Offset0 //INSN_A<o:p></o:p></p></div><div><p class=MsoNormal> ... ...<o:p></o:p></p></div><div><p class=MsoNormal> STORE Reg3, Reg2 + Offset2 //INSN_B<o:p></o:p></p></div><div><p class=MsoNormal>If INSN_A-->INSN_B(<b>store-->store</b>) had mem order dependence inside the iteration(Assuming that alias analysis result for the addresses Reg0 + Offset0/Reg2 + Offset2 were dependent)<o:p></o:p></p></div><div><p class=MsoNormal>For cross iteration dependence, INSN_B-->INSN_A must have mem order dependence too.<o:p></o:p></p></div><div><p class=MsoNormal>So I wonder why in current implementation of swp, there're no enough mem loop carried dependence? will it cause some correct problems?<o:p></o:p></p></div><div><p class=MsoNormal>Also, I checked SMS pass in GCC, and found that DDG graph will construct correct cross iteration memory dependence(store-->load, load-->store, store-->store)<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Thanks,<o:p></o:p></p></div><div><p class=MsoNormal>Wei Wei<o:p></o:p></p></div></div></div></body></html>