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<div class="moz-cite-prefix">On 8/11/2017 10:56 PM, Kerbow, Austin
Michael via llvm-dev wrote:<br>
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I am working on a project where we are integrating an existing
pre-RA scheduler into LLVM and we are trying to match our peak
register pressure values with the machine instruction schedulers
values while using X86. I am finding some mismatches in test
cases like the one attached. The registers "AH" and "AL" are
live-out but not live-in and I don't see that they are defined
in the block when walking through the operands for these
instructions. The peak pressure printouts from ScheduleDAGMILive
look like they are accounting for AH and AL being live because
the corresponding pressure sets for these register classes are
increased. In the mischeduler is there a way to discover that
these two registers may be contributing to peak pressure in the
block?</div>
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AL and AH are subregisters of RAX.<br>
<br>
-Eli<br>
<pre class="moz-signature" cols="72">--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project</pre>
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