<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40">
<head>
<meta http-equiv="Content-Type" content="text/html; charset=us-ascii">
<meta name="Generator" content="Microsoft Word 15 (filtered medium)">
<style><!--
/* Font Definitions */
@font-face
{font-family:"Cambria Math";
panose-1:2 4 5 3 5 4 6 3 2 4;}
@font-face
{font-family:Calibri;
panose-1:2 15 5 2 2 2 4 3 2 4;}
/* Style Definitions */
p.MsoNormal, li.MsoNormal, div.MsoNormal
{margin:0in;
margin-bottom:.0001pt;
font-size:11.0pt;
font-family:"Calibri",sans-serif;}
a:link, span.MsoHyperlink
{mso-style-priority:99;
color:blue;
text-decoration:underline;}
a:visited, span.MsoHyperlinkFollowed
{mso-style-priority:99;
color:purple;
text-decoration:underline;}
span.EmailStyle17
{mso-style-type:personal-compose;
font-family:"Calibri",sans-serif;
color:windowtext;}
.MsoChpDefault
{mso-style-type:export-only;
font-family:"Calibri",sans-serif;}
@page WordSection1
{size:8.5in 11.0in;
margin:1.0in 1.0in 1.0in 1.0in;}
div.WordSection1
{page:WordSection1;}
--></style><!--[if gte mso 9]><xml>
<o:shapedefaults v:ext="edit" spidmax="1026" />
</xml><![endif]--><!--[if gte mso 9]><xml>
<o:shapelayout v:ext="edit">
<o:idmap v:ext="edit" data="1" />
</o:shapelayout></xml><![endif]-->
</head>
<body lang="EN-US" link="blue" vlink="purple">
<div class="WordSection1">
<p class="MsoNormal">Hello,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">We at Synopsys would like to propose integration of a backend targeting<o:p></o:p></p>
<p class="MsoNormal">the Synopsys ARC architecture. ARC is a configurable 32-bit processor<o:p></o:p></p>
<p class="MsoNormal">family with a variety of optional extensions.<o:p></o:p></p>
<p class="MsoNormal">See:<o:p></o:p></p>
<p class="MsoNormal">https://www.synopsys.com/designware-ip/processor-solutions/arc-processors.html<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">We have been using LLVM internally for a number of years. The current<o:p></o:p></p>
<p class="MsoNormal">plan, if accepted by the community, is to contribute an minimal,<o:p></o:p></p>
<p class="MsoNormal">functional backend that would be an experimental target while we<o:p></o:p></p>
<p class="MsoNormal">incrementally add features until we have a more fully featured backend.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">About ARC:<o:p></o:p></p>
<p class="MsoNormal">* There are two currently supported ISA versions supported by gcc, v1 and v2.<o:p></o:p></p>
<p class="MsoNormal">* The ARC ISA is a mixed 32-/16-bit ISA.<o:p></o:p></p>
<p class="MsoNormal">* Has both big and little endian modes.<o:p></o:p></p>
<p class="MsoNormal">* Individual instructions may have different variants and encodings.<o:p></o:p></p>
<p class="MsoNormal">* Is configurable with a number of instructions that can be configured<o:p></o:p></p>
<p class="MsoNormal"> in or out of a particular processor configuration.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">The current proposed submission:<o:p></o:p></p>
<p class="MsoNormal">* Only targets ARC v2.<o:p></o:p></p>
<p class="MsoNormal">* Includes a small functional subset of the 32-bit ISA, little endian.<o:p></o:p></p>
<p class="MsoNormal">* Targets a fixed subset of the ARC v2 ISA.<o:p></o:p></p>
<p class="MsoNormal">* Focuses on C99 support.<o:p></o:p></p>
<p class="MsoNormal">* Implements Target registration, and a SelectionDAG based instruction selector.<o:p></o:p></p>
<p class="MsoNormal">* Implements Register and the ISA specification for current subset.<o:p></o:p></p>
<p class="MsoNormal">* Implements the Assembly printer and disassembler.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">See:<o:p></o:p></p>
<p class="MsoNormal"><a href="https://reviews.llvm.org/D36331">https://reviews.llvm.org/D36331</a><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Following shortly:<o:p></o:p></p>
<p class="MsoNormal">* Clang driver and target triple support.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Planned:<o:p></o:p></p>
<p class="MsoNormal">* C++ (Exception Handling).<o:p></o:p></p>
<p class="MsoNormal">* Assembly Parsing/Direct ELF emission.<o:p></o:p></p>
<p class="MsoNormal">* GlobalISel.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">With community agreement, our plan is to:<o:p></o:p></p>
<p class="MsoNormal">1. Contribute the current fixed configuration target.<o:p></o:p></p>
<p class="MsoNormal">2. Incrementally add the currently missing variants<o:p></o:p></p>
<p class="MsoNormal"> and additional instructions for this fixed target.<o:p></o:p></p>
<p class="MsoNormal">3. Add support for different ARC configurations and<o:p></o:p></p>
<p class="MsoNormal"> target specific features.<o:p></o:p></p>
<p class="MsoNormal">4. Implement the planned features from the LLVM framework<o:p></o:p></p>
<p class="MsoNormal"> not specific to ARC.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Thanks for reading this far, feedback and comments welcome!<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Pete<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
</div>
</body>
</html>