<div dir="ltr">Thank you for a your reply.<div>No i am not asking for software pipelining. my goal is different.</div><div><br></div><div>I am targetting a hardware with 64 element vector operations. now there are 2 scenarios;</div><div><br></div><div>if my loop has >=2048 iterations i use vector width=2048 and if my loop has <2048 iterations i use vector width=64. but my hardware doesnot support vector width=2048 it does support vector width=64. </div><div>now when iterations >=2048, again they are splitted into v64i32( have implemented it). till this point instruction selection is working fine.</div><div>the only difference should come in register set. the registers are same for both the scenarios but their ordering is need to be different like;</div><div>if no of iterations >=2048, ordering should be of Reg_A</div><div><blockquote type="cite"><div class="gmail-h5"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div class="gmail-m_5991332674792446810HOEnZb"><div class="gmail-m_5991332674792446810h5"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div class="gmail-m_5991332674792446810m_4996687047443152407HOEnZb"><div class="gmail-m_5991332674792446810m_4996687047443152407h5"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr"><div>R_0_V_0, R_0_V_1, R_0_V_2, R_0_V_3,</div><div>R_1_V_0, R_1_V_1, R_1_V_2, R_1_V_3,</div><div>R_2_V_0, R_2_V_1, R_2_V_2, R_2_V_3.</div><div>These registers defined in object Reg_A</div></div></blockquote></div></div></div></div></blockquote></div></div></div></div></blockquote></div></div></div></blockquote></div><div>here;</div><div><blockquote type="cite"><div class="gmail-h5"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div class="gmail-m_5991332674792446810HOEnZb"><div class="gmail-m_5991332674792446810h5"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div class="gmail-m_5991332674792446810m_4996687047443152407HOEnZb"><div class="gmail-m_5991332674792446810m_4996687047443152407h5"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr"><div>1st load will take place in R_0_V_0</div><div>2nd load will take place in R_0_V_1</div><div>3rd load will take place in R_0_V_2</div><div>4th load will take place in R_0_V_3</div></div></blockquote></div></div></div></div></blockquote></div></div></div></div></blockquote></div></div></div></blockquote></div><div><br></div><div><div>if no of iterations <2048, ordering should be of Reg_B</div><div><blockquote type="cite"><div class="gmail-h5"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div class="gmail-m_5991332674792446810HOEnZb"><div class="gmail-m_5991332674792446810h5"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div class="gmail-m_5991332674792446810m_4996687047443152407HOEnZb"><div class="gmail-m_5991332674792446810m_4996687047443152407h5"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr"></div></blockquote></div></div></div></div></blockquote></div></div></div></div></blockquote></div></div></div></blockquote></div></div><div><blockquote type="cite"><div class="gmail-h5"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div class="gmail-m_5991332674792446810HOEnZb"><div class="gmail-m_5991332674792446810h5"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div class="gmail-m_5991332674792446810m_4996687047443152407HOEnZb"><div class="gmail-m_5991332674792446810m_4996687047443152407h5"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr"><div>Reg_B;</div><div><br></div><div><div>R_0_V_0, R_1_V_0, R_2_V_0, //here R changes</div><div>R_0_V_1, R_1_V_1, R_2_V_1, </div><div>R_0_V_2, R_1_V_2, R_2_V_2, </div></div><div>R_0_V_3, R_1_V_3, R_2_V_3.</div></div></blockquote></div></div></div></div></blockquote></div></div></div></div></blockquote><div>here</div><div><br></div><div>1st load to take place in R_0_V_0<br></div></div></div></div></blockquote><blockquote type="cite"><div class="gmail-h5"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div class="gmail-m_5991332674792446810HOEnZb"><div class="gmail-m_5991332674792446810h5"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div class="gmail-m_5991332674792446810m_4996687047443152407HOEnZb"><div class="gmail-m_5991332674792446810m_4996687047443152407h5"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr"><div>2nd load to take place in R_1_V_0</div></div></blockquote></div></div></div></div></blockquote></div></div></div></div></blockquote></div></div></div></blockquote><blockquote type="cite"><div class="gmail-h5"><div class="gmail_extra"><div class="gmail_quote"><div>3rd load to take place in R_2_V_0 </div></div></div></div></blockquote></div><div><br></div><div>here i need is this that if no of iterations<2048 and i set vector width=64 then in this case i want my operations to be performed on Reg_B if iterations>=2048, operations to be performed on Reg_A.</div><div><br></div><div>i have think of several solutions to this but none worked yet??</div><div><br></div><div>can it be something like;</div><div><br></div><div>i provide support for v2048i32 in llvm and then use expand like this;</div><div><br></div><div> setOperationAction(ISD::LOAD , MVT::v2048i32 , Expand);</div><div><br></div><div>so that it can split v2048i32 into v64i32 and in <a href="http://instructioninfo.td">instructioninfo.td</a> i associate reg_a with it instead of reg_b there in <a href="http://instructioninfo.td">instructioninfo.td</a> i will use v2048i32 for >=2048 iterations and v64i32 for <2048 iterations but that v2048i32 is required to be lowered to v64i32 (in isellowering.cpp) because no support for v2048i32 in hardware. so i will use v2048i32 here just to distinguish no of iterations...</div><div><br></div><div>What do you say??</div><div>please help. i am seriously stuck here.</div><div><br></div><div>Thank you</div><div><br></div><div><br></div><div> <br><div><br></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jul 11, 2017 at 7:48 AM, Matthias Braun <span dir="ltr"><<a href="mailto:mbraun@apple.com" target="_blank">mbraun@apple.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div style="word-wrap:break-word"><div>Are you asking for software pipelining? There is a MachinePipeliner pass that targets can put into their pass pipeline.</div><div><br></div><div>- Matthias</div><div><br></div><div><blockquote type="cite"><div><div class="gmail-h5"><div>On Jul 10, 2017, at 3:46 AM, hameeza ahmed via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>> wrote:</div><br class="gmail-m_5991332674792446810Apple-interchange-newline"></div></div><div><div><div class="gmail-h5"><div dir="ltr">can someone suggest me solution for this problem??<div>Need serious help. My work is stuck............</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Jul 10, 2017 at 10:22 AM, hameeza ahmed <span dir="ltr"><<a href="mailto:hahmed2305@gmail.com" target="_blank">hahmed2305@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr">Here basically my problem is vector width since i have used v64i32 in my backend. now if vector width=64. i want the Reg_B class registers to be assigned and if vector width=2048 i want Reg_A registers to be assigned to instruction. <div><br></div><div>Should i incorporate the solution in lowering stage? some thing like;</div><div><br></div><div>addRegisterClass(MVT::v2048i32<wbr>, &X86::Reg_B);<br></div><div><br></div><div><div> setOperationAction(ISD::MNLOAD<wbr>, MVT::v2048i32, custom);</div></div><div><br></div><div>then in function LowerOperation(SDValu<wbr>e Op, SelectionDAG &DAG)</div><div><br></div><div>i should do,</div><div><br></div><div><div> case ISD::MNLOAD: return LOAD2048(Op, Subtarget, DAG);</div></div><div><br></div><div>then i will implement</div><div><div>static SDValue LOAD2048(SDValue Op, const X86Subtarget &Subtarget,</div><div> SelectionDAG &DAG)</div></div><div>{</div><div><br></div><div>//dont know the details of this part</div><div>but here i plan to encode 2048 elements again in 32 v64i32 but with different instruction name like previously it was </div><div>load<LD256; i intend to make it load<LD256_N<br></div><div><br></div><div>so that in <a href="http://instructioninfo.td/" target="_blank">instructioninfo.td</a> while pattern matching both LD256 and LD256_N are treated separately. 1 will use Reg_B registers and other will use Reg_A respectively.</div><div><br></div><div><br></div><div>Is it fine??? </div><div>Please guide me...</div><div>I need serious help, please.....</div><div><br></div><div>Thank You</div><div><br></div><div><br></div></div><div class="gmail-m_5991332674792446810HOEnZb"><div class="gmail-m_5991332674792446810h5"><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Jul 10, 2017 at 9:29 AM, hameeza ahmed <span dir="ltr"><<a href="mailto:hahmed2305@gmail.com" target="_blank">hahmed2305@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr">or should i write a condition in <a href="http://registerinfo.td/" target="_blank">registerinfo.td</a>; to define the registers in object Reg_A in specific order according to loop iterations.</div><div class="gmail-m_5991332674792446810m_4996687047443152407HOEnZb"><div class="gmail-m_5991332674792446810m_4996687047443152407h5"><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Jul 10, 2017 at 9:17 AM, hameeza ahmed <span dir="ltr"><<a href="mailto:hahmed2305@gmail.com" target="_blank">hahmed2305@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr">hello,<div><br></div><div>i have a situation where i have to assign the registers to instructions based on the loop iterations.</div><div><br></div><div>for eg.. </div><div>the registers are: </div><div>R_0_V_0, R_0_V_1, R_0_V_2, R_0_V_3,</div><div><div>R_1_V_0, R_1_V_1, R_1_V_2, R_1_V_3,</div></div><div><div>R_2_V_0, R_2_V_1, R_2_V_2, R_2_V_3.</div></div><div>These registers defined in object Reg_A</div><div><br></div><div>These are total 12 registers. will use them contiguously, here i define it in above mentioned order i.e changing V first then R.</div><div><br></div><div><br></div><div>for eg;</div><div>if no of iterations>=4.</div><div>1st load will take place in R_0_V_0</div><div><div>2nd load will take place in R_0_V_1</div></div><div><div>3rd load will take place in R_0_V_2</div></div><div><div>4th load will take place in R_0_V_3</div></div><div>I am getting this required behavior for iterations>=4. I want this to happen only if there are 4 or above iterations in loop.</div><div><br></div><div><br></div><div>But if my iterations are less than 4 like 3</div><div>again it will do the same thing;</div><div><div>1st load will take place in R_0_V_0</div><div>2nd load will take place in R_0_V_1</div><div>3rd load will take place in R_0_V_2</div></div><div><br></div><div>Here i dont want the above to happen rather it should increment R instead of V in this case.</div><div>It should do something as follows:</div><div>1st load to take place in R_0_V_0</div><div><div>2nd load to take place in R_1_V_0</div><div>3rd load to take place in R_2_V_0</div></div><div><br></div><div>Now, how to achieve this?</div><div><br></div><div>Can i mention some condition in <a href="http://instructioninfo.td/" target="_blank">instructioninfo.td</a> file? </div><div>and in <a href="http://registerinfo.td/" target="_blank">registerinfo.td</a> file instead of 1 object Reg_A, there will be 2 objects Reg_A and Reg_B</div><div>where Reg_B defines same registers but in different order.</div><div><br></div><div>Reg_B;</div><div><br></div><div><div>R_0_V_0, R_1_V_0, R_2_V_0, //here R changes</div><div>R_0_V_1, R_1_V_1, R_2_V_1, </div><div>R_0_V_2, R_1_V_2, R_2_V_2, </div></div><div>R_0_V_3, R_1_V_3, R_2_V_3.</div><div><br></div><div>So that in <a href="http://instructioninfo.td/" target="_blank">instructioninfo.td</a> file it will be something like;</div><div><br></div><div>if (no of iterations>=4)</div><div><br></div><div>load ................$Reg_A ; here all register operands will come from Reg_A instance.</div><div><br></div><div><div>if (no of iterations<4)</div><div><br></div><div>load ................$Reg_B ; here all register operands will come from Reg_B instance.</div></div><div><br></div><div><br></div><div>Is the above approach possible??? if yes then how can we acquire the no of iterations in <a href="http://instructioninfo.td/" target="_blank">instructioninfo.td</a> file??</div><div><br></div><div>or can you suggest some better way?</div><div><br></div><div>Looking forward to response</div><div><br></div><div>Thank You.</div><div><br></div><div><br></div><div><br></div></div>
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