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<div class="moz-cite-prefix">Have you read
<a class="moz-txt-link-freetext" href="http://llvm.org/docs/WritingAnLLVMBackend.html">http://llvm.org/docs/WritingAnLLVMBackend.html</a> and
<a class="moz-txt-link-freetext" href="http://llvm.org/docs/CodeGenerator.html">http://llvm.org/docs/CodeGenerator.html</a> ?
<a class="moz-txt-link-freetext" href="http://llvm.org/docs/WritingAnLLVMBackend.html#instruction-selector">http://llvm.org/docs/WritingAnLLVMBackend.html#instruction-selector</a>
describes how to define a store instruction.<br>
<br>
-Eli<br>
<br>
On 7/6/2017 6:51 PM, hameeza ahmed via llvm-dev wrote:<br>
</div>
<blockquote type="cite"
cite="mid:CAFMPKeYEX1hXut94smpguLa4sBGsg93_9CrX7YG6WqAJHi28Bw@mail.gmail.com">
<div dir="auto">
<div>Please correct me i m stuck at this point.<br>
<div class="gmail_extra"><br>
<div class="gmail_quote">On Jul 6, 2017 5:18 PM, "hameeza
ahmed" <<a href="mailto:hahmed2305@gmail.com"
moz-do-not-send="true">hahmed2305@gmail.com</a>>
wrote:<br type="attribution">
<blockquote class="quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex">
<div dir="ltr">Hello,
<div>i am experimenting with the increase in register/
vector width to 64 elements of 32 bits instead of 16
in x86 backend. </div>
<div>for eg.</div>
<div>i have a loop with 65 iterations;</div>
<div>if my IR generates v64i32 and 1 scalar, still the
backend breaks the v64i32 into 4 v16i32. i want it
to retain v64i32. like if there are 128 elements in
loop then it should break it into 2 v64i32
instructions.</div>
<div><br>
</div>
<div>in order to do this i have made necessary changes
in X86ISelLowering.cpp. and rebuild llvm. then when
i use the command -view-dag-combine2-<wbr>dags i get
the required output in graph but the following error
on console:</div>
<div><br>
</div>
<div>
<div>LLVM ERROR: Cannot select: t10: ch =
store<ST256[bitcast ([65 x i32]* @a to <64 x
i32>*)](align=16)(tbaa=<<wbr>0x30c5438>)>
t9, t7, t12, undef:i64</div>
<div> t7: v64i32 = add t6, t4</div>
<div> t6: v64i32,ch = load<LD256[bitcast ([65
x i32]* @c to <64 x
i32>*)](align=16)(tbaa=<<wbr>0x30c5438>)(dereferenceable)>
t0, t14, undef:i64</div>
<div> t14: i64 = X86ISD::Wrapper
TargetGlobalAddress:i64<[65 x i32]* @c> 0</div>
<div> t13: i64 = TargetGlobalAddress<[65 x
i32]* @c> 0</div>
<div> t3: i64 = undef</div>
<div> t4: v64i32,ch = load<LD256[bitcast ([65
x i32]* @b to <64 x
i32>*)](align=16)(tbaa=<<wbr>0x30c5438>)(dereferenceable)>
t0, t16, undef:i64</div>
<div> t16: i64 = X86ISD::Wrapper
TargetGlobalAddress:i64<[65 x i32]* @b> 0</div>
<div> t15: i64 = TargetGlobalAddress<[65 x
i32]* @b> 0</div>
<div> t3: i64 = undef</div>
<div> t12: i64 = X86ISD::Wrapper
TargetGlobalAddress:i64<[65 x i32]* @a> 0</div>
<div> t11: i64 = TargetGlobalAddress<[65 x
i32]* @a> 0</div>
<div> t3: i64 = undef</div>
<div>In function: foo</div>
</div>
<div><br>
</div>
<div>The dag after legalization is also attached here.</div>
<div><br>
</div>
<div>the source is vector sum of 65 elements.</div>
<div><br>
</div>
<div><br>
</div>
<div>Kindly correct me.</div>
</div>
</blockquote>
</div>
<br>
</div>
</div>
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<br>
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</pre>
</blockquote>
<p><br>
</p>
<pre class="moz-signature" cols="72">--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project</pre>
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