<div dir="ltr">Yes, that error is from instruction selection. I think your legalization changes worked fine.</div><div class="gmail_extra"><br clear="all"><div><div class="gmail_signature" data-smartmail="gmail_signature">~Craig</div></div>
<br><div class="gmail_quote">On Thu, Jul 6, 2017 at 8:21 PM, hameeza ahmed via llvm-dev <span dir="ltr"><<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">also i further run the following command;<div>llc -debug filer-knl_o3.ll<br></div><div><br></div><div>and its output is attached here. by looking at the output can we say that legalization runs fine and the error is due to instruction selection/ pattern matching which is not yet implemented?</div><div><br></div><div>so do i need to worry and try to correct it at this stage or should i move forward to implement instruction selection/ pattern matching?</div><div><br></div><div>Please guide me.</div><div><br></div><div>Thank You</div></div><div class="HOEnZb"><div class="h5"><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Jul 7, 2017 at 8:00 AM, hameeza ahmed <span dir="ltr"><<a href="mailto:hahmed2305@gmail.com" target="_blank">hahmed2305@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Thank You. well i have seen these links. but they dont cover the problem that i have mentioned. actually i am doing all the things step by step.<div><br></div><div>so i havent yet worked with instruction selection phase/ files. rather before that i am trying to do legalization by allowing vector elements>16 i.e 64xi32. here i have mainly worked with 2 files uptil now, i.e <a href="http://registerinfo.td" target="_blank">registerinfo.td</a> to define register class to be called in legalization. and most importantly i am dealing with file <span style="font-size:12.8px">X86ISelLowering.cpp.</span></div><div><span style="font-size:12.8px"><br></span></div><div><span style="font-size:12.8px">Now is there any relation in this and instruction selection. since instruction selection comes after combine and legalize so i havent yet worked on it.</span></div><div><span style="font-size:12.8px"><br></span></div><div><span style="font-size:12.8px"><br></span></div><div><span style="font-size:12.8px">Please correct me, I am stuck here.</span></div><div><span style="font-size:12.8px"><br></span></div><div><span style="font-size:12.8px">Thank You again</span></div></div><div class="m_3376525912337003014HOEnZb"><div class="m_3376525912337003014h5"><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Jul 7, 2017 at 7:11 AM, Friedman, Eli <span dir="ltr"><<a href="mailto:efriedma@codeaurora.org" target="_blank">efriedma@codeaurora.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div text="#000000" bgcolor="#FFFFFF">
<div class="m_3376525912337003014m_1036672289896603809m_-3066541527091829227moz-cite-prefix">Have you read
<a class="m_3376525912337003014m_1036672289896603809m_-3066541527091829227moz-txt-link-freetext" href="http://llvm.org/docs/WritingAnLLVMBackend.html" target="_blank">http://llvm.org/docs/WritingAn<wbr>LLVMBackend.html</a> and
<a class="m_3376525912337003014m_1036672289896603809m_-3066541527091829227moz-txt-link-freetext" href="http://llvm.org/docs/CodeGenerator.html" target="_blank">http://llvm.org/docs/CodeGener<wbr>ator.html</a> ?
<a class="m_3376525912337003014m_1036672289896603809m_-3066541527091829227moz-txt-link-freetext" href="http://llvm.org/docs/WritingAnLLVMBackend.html#instruction-selector" target="_blank">http://llvm.org/docs/WritingAn<wbr>LLVMBackend.html#instruction-s<wbr>elector</a>
describes how to define a store instruction.<br>
<br>
-Eli<div><div class="m_3376525912337003014m_1036672289896603809h5"><br>
<br>
On 7/6/2017 6:51 PM, hameeza ahmed via llvm-dev wrote:<br>
</div></div></div>
<blockquote type="cite"><div><div class="m_3376525912337003014m_1036672289896603809h5">
<div dir="auto">
<div>Please correct me i m stuck at this point.<br>
<div class="gmail_extra"><br>
<div class="gmail_quote">On Jul 6, 2017 5:18 PM, "hameeza
ahmed" <<a href="mailto:hahmed2305@gmail.com" target="_blank">hahmed2305@gmail.com</a>>
wrote:<br type="attribution">
<blockquote class="m_3376525912337003014m_1036672289896603809m_-3066541527091829227quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div dir="ltr">Hello,
<div>i am experimenting with the increase in register/
vector width to 64 elements of 32 bits instead of 16
in x86 backend. </div>
<div>for eg.</div>
<div>i have a loop with 65 iterations;</div>
<div>if my IR generates v64i32 and 1 scalar, still the
backend breaks the v64i32 into 4 v16i32. i want it
to retain v64i32. like if there are 128 elements in
loop then it should break it into 2 v64i32
instructions.</div>
<div><br>
</div>
<div>in order to do this i have made necessary changes
in X86ISelLowering.cpp. and rebuild llvm. then when
i use the command -view-dag-combine2-dag<wbr>s i get
the required output in graph but the following error
on console:</div>
<div><br>
</div>
<div>
<div>LLVM ERROR: Cannot select: t10: ch =
store<ST256[bitcast ([65 x i32]* @a to <64 x
i32>*)](align=16)(tbaa=<0x30c5<wbr>438>)>
t9, t7, t12, undef:i64</div>
<div> t7: v64i32 = add t6, t4</div>
<div> t6: v64i32,ch = load<LD256[bitcast ([65
x i32]* @c to <64 x
i32>*)](align=16)(tbaa=<0x30c5<wbr>438>)(dereferenceable)>
t0, t14, undef:i64</div>
<div> t14: i64 = X86ISD::Wrapper
TargetGlobalAddress:i64<[65 x i32]* @c> 0</div>
<div> t13: i64 = TargetGlobalAddress<[65 x
i32]* @c> 0</div>
<div> t3: i64 = undef</div>
<div> t4: v64i32,ch = load<LD256[bitcast ([65
x i32]* @b to <64 x
i32>*)](align=16)(tbaa=<0x30c5<wbr>438>)(dereferenceable)>
t0, t16, undef:i64</div>
<div> t16: i64 = X86ISD::Wrapper
TargetGlobalAddress:i64<[65 x i32]* @b> 0</div>
<div> t15: i64 = TargetGlobalAddress<[65 x
i32]* @b> 0</div>
<div> t3: i64 = undef</div>
<div> t12: i64 = X86ISD::Wrapper
TargetGlobalAddress:i64<[65 x i32]* @a> 0</div>
<div> t11: i64 = TargetGlobalAddress<[65 x
i32]* @a> 0</div>
<div> t3: i64 = undef</div>
<div>In function: foo</div>
</div>
<div><br>
</div>
<div>The dag after legalization is also attached here.</div>
<div><br>
</div>
<div>the source is vector sum of 65 elements.</div>
<div><br>
</div>
<div><br>
</div>
<div>Kindly correct me.</div>
</div>
</blockquote>
</div>
<br>
</div>
</div>
</div>
<br>
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