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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt'>Hi Ehsan,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt'>> </span><span style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'>If we see these kind of copies frequently enough, do you think it is worthwhile to work on the algorithm, so these instructions are predicted and taken into account during the scheduling?<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt'>if you do see them frequently, then it would be worthwhile to find a way to eliminate them. I’m not sure how easy it would be to predict them though when the MII is computed. My guess is that you want some solution where the generated schedule doesn’t require the extra copies. Without some more information, it’s hard to see why the algorithm is generating a schedule that requires extra copies so frequently.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt'><o:p> </o:p></span></p><p class=MsoNormal align=left style='text-align:left'><span style='font-size:11.0pt'>> </span><span style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'>Or maybe we already do this and I am not aware of it?<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt'>In some cases, the pipeliner does attempt to eliminate unnecessary copies. For Hexagon, or any machine that allows multiple instructions per cycle, the pipeliner attempts to order the generated instructions to minimize copies. For example, Hexagon allows up to 4 instructions to execute “in parallel”. So, in the same cycle, there can be a use of a register and a definition of that same register (the uses are read first, then the definition occurs). In effect, the use is for the value generated in the previous iteration. Since the pipeliner generates a linear list of instructions (i.e., serial semantics), the final order needs to make sure that the use is generated before the definition. Otherwise, an extra copy is generated.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt'><o:p> </o:p></span></p><p class=MsoNormal align=left style='text-align:left'><span style='font-size:11.0pt'>> </span><span style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'>IIUC, these kind of copies will be generated even if we implement SMS after register coalescing. Is this correct?<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt'>That is correct.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'>> you don’t see it frequently though. Is that correct?</span><span style='font-size:11.0pt'><o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt'>Correct. For Hexagon, we don’t see the extra copies very frequently. In your earlier example though, it would be interesting to see why the algorithm puts the definition prior to the last use. If possible, its better to schedule the definition after the last use. Of course, in some cases, that may/may not generate an efficient schedule.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt'>Thanks,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt'>Brendon<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt'><o:p> </o:p></span></p><div><div style='border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal align=left style='text-align:left'><b><span style='font-size:11.0pt'>From:</span></b><span style='font-size:11.0pt'> Ehsan Amiri [mailto:ehsan.amiri@huawei.com] <br><b>Sent:</b> Tuesday, June 27, 2017 7:57 AM<br><b>To:</b> Brendon Cahoon <bcahoon@codeaurora.org><br><b>Cc:</b> llvm-dev@lists.llvm.org<br><b>Subject:</b> RE: [llvm-dev] Some questions about software pipeline in LLVM 4.0.0<o:p></o:p></span></p></div></div><p class=MsoNormal align=left style='text-align:left'><o:p> </o:p></p><div><p class=MsoNormal align=left style='text-align:left'><span style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'>Hi Brendon <o:p></o:p></span></p><div><p class=MsoNormal align=left style='text-align:left'><span style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'><o:p> </o:p></span></p></div><div><p class=MsoNormal align=left style='text-align:left'><span style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'>Thanks for the answer. I completely agree with your comments. The main reason that I brought up this issue is the following: Inserting a COPY instruction that cannot be eliminated, means that the loop has an instruction that was not taken into account during modulo scheduling analysis. If we see these kind of copies frequently enough, do you think it is worthwhile to work on the algorithm, so these instructions are predicted and taken into account during the scheduling? Or maybe we already do this and I am not aware of it?<o:p></o:p></span></p></div><div><p class=MsoNormal align=left style='text-align:left'><span style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'><o:p> </o:p></span></p><p class=MsoNormal align=left style='text-align:left'><span style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'>Some other remarks/questions:<o:p></o:p></span></p><p class=MsoNormal align=left style='text-align:left'><span style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'><o:p> </o:p></span></p><p class=MsoNormal align=left style='text-align:left'><span style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'>IIUC, these kind of copies will be generated even if we implement SMS after register coalescing. Is this correct?<o:p></o:p></span></p><p class=MsoNormal align=left style='text-align:left'><span style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'><o:p> </o:p></span></p><p class=MsoNormal align=left style='text-align:left'><span style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'>For us, so far we have enabled machine pipeliner for our backend and we see these kind of copy generated frequently for our workloads. Some times multiple copies inserted in a relatively small loop. IIUC, you don’t see it frequently though. Is that correct?<o:p></o:p></span></p><p class=MsoNormal align=left style='text-align:left'><span style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'><o:p> </o:p></span></p><p class=MsoNormal align=left style='text-align:left'><span style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'>Thanks<o:p></o:p></span></p><p class=MsoNormal align=left style='text-align:left'><span style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'>Ehsan<o:p></o:p></span></p><p class=MsoNormal align=left style='text-align:left'><span style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'><o:p> </o:p></span></p></div><div><p class=MsoNormal align=left style='text-align:left'><span style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'><o:p> </o:p></span></p></div><div><div><div><div><p class=MsoNormal><span style='color:black'><o:p> </o:p></span></p></div></div></div></div></div></div></body></html>