<div dir="ltr"><div>I'll attempt to answer some of the questions.</div><div><br></div>Using a few registers by itself isn't necessarily going to prevent performance. Modern processors implement what's known as register renaming internally. Each time a register is written to the processor allocates one of nearly 200 internal registers to hold the result of the computation. Each time a register like xmm0 is read by an instruction the processor looks up in a table to see which internal register was last assigned to xmm0. This tells the instruction to read that internal register to get the value of xmm0. So if there are a lot of independent calculations its perfectly fine to use only a few registers because the processor will remap them to a much larger set internally. Out of the 200 internal registers only a few of them have a name(xmm0, xmm1, etc) accessible to software at any point in the code. Having more named registers allows you to have a lot of values "live" at a particular point in a program.<div><br></div><div>Although each core has an AVX unit, a single "thread" of a program is only able to use one core. Using the other cores requires the developer to write special code to create additional threads and give them their own work to do. The cost of moving data between cores is quite high so these multithread tasks need to be pretty indepenent.</div><div><br></div><div>Within a thread a processor can theoretically execute up to about 6 or so instructions simultaneously. But those 6 instructions are handled by units of the cpu designed for different tasks. For example a couple of those units only handle loads and stores. While others only handle arithmetic instructions. So to execute the maximum number of instructions in parallel you need the right mix of operations. And even the units that handle arithmetic instructions aren't created equal. For example, there is only one unit that can handle a divide operation and that keeps the divider busy for 10s of cycles.</div><div><br></div><div>rip-relative addressing isn't specific to position independent code. In fact I believe x86-64 is always position independent because it always uses rip-relative addressing. There only a few instructions that can take a full 64-bit constant address. So rip relative addressing is used for things like global variables and constant tables. The assumption is that the code and data are with 2gb of each other in the address space and always in the same layout so you can use a fixed offset from the current instruction pointer(the ip in rip stands for instruction pointer) to access the data. This results in a smaller encoding than if you needed a full 64-bit offset. </div></div><div class="gmail_extra"><br clear="all"><div><div class="gmail_signature" data-smartmail="gmail_signature">~Craig</div></div>
<br><div class="gmail_quote">On Fri, Jun 23, 2017 at 7:25 PM, hameeza ahmed via llvm-dev <span dir="ltr"><<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><br><div class="gmail_quote">---------- Forwarded message ----------<br>From: <b class="gmail_sendername">hameeza ahmed</b> <span dir="ltr"><<a href="mailto:hahmed2305@gmail.com" target="_blank">hahmed2305@gmail.com</a>></span><br>Date: Sat, Jun 24, 2017 at 7:21 AM<br>Subject: Re: [llvm-dev] AVX Scheduling and Parallelism<br>To: Hal Finkel <<a href="mailto:hfinkel@anl.gov" target="_blank">hfinkel@anl.gov</a>><br><br><br><div dir="ltr"><div>int a[100351], b[100351], c[100351];</div><div>foo () {</div><div>int i;</div><div>for (i=0; i<100351; i++) {</div><div>a[i] = b[i] + c[i];</div><div>}</div><div>}</div></div><div><div class="h5"><div class="m_-5033067552900698344HOEnZb"><div class="m_-5033067552900698344h5"><div class="gmail_extra"><br><div class="gmail_quote">On Sat, Jun 24, 2017 at 7:16 AM, Hal Finkel <span dir="ltr"><<a href="mailto:hfinkel@anl.gov" target="_blank">hfinkel@anl.gov</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div bgcolor="#FFFFFF" text="#000000">
<p>It is possible that the issue with scheduling is constrained due
to pointer-aliasing assumptions. Could you share the source for
the loop in question?</p>
<p>RIP-relative indexing, as I recall, is a feature of
position-independent code. Based on what's below, it might cause
problems by making the instruction encodings large. cc'ing some
Intel folks for further comments.</p>
<p> -Hal<br>
</p><div><div class="m_-5033067552900698344m_-1589879501904212397h5">
<div class="m_-5033067552900698344m_-1589879501904212397m_7604358723266123794moz-cite-prefix">On 06/23/2017 09:02 PM, hameeza ahmed
via llvm-dev wrote:<br>
</div>
</div></div><blockquote type="cite"><div><div class="m_-5033067552900698344m_-1589879501904212397h5">
<div dir="ltr">Hello,
<div><br>
</div>
<div>After generating AVX code for large no of iterations i came
to realize that it still uses only 2 registers zmm0 and zmm1
when the loop urnroll factor=1024,</div>
<div><br>
</div>
<div>i wonder if this register allocation allows operations in
parallel?</div>
<div><br>
</div>
<div>Also i know all the elements within a single vector
instruction are computed in parallel but does the elements of
multiple instructions computed in parallel? like are 2 vmov
with different registers executed in parallel? it can be
because each core has an AVX unit. does compiler exploit it?</div>
<div><br>
</div>
<div><br>
</div>
<div>secondly i am generating assembly for intel and there are
some offset like rip register or some constant addition in
memory index. why is that so?</div>
<div>eg.1</div>
<div><br>
</div>
<div>
<div><span style="white-space:pre-wrap"> </span>vmovdqu32<span style="white-space:pre-wrap"> </span>zmm0,
zmmword ptr [rip + c]</div>
<div><span style="white-space:pre-wrap"> </span>vpaddd<span style="white-space:pre-wrap"> </span>zmm0,
zmm0, zmmword ptr [rip + b]</div>
<div><span style="white-space:pre-wrap"> </span>vmovdqu32<span style="white-space:pre-wrap"> </span>zmmword
ptr [rip + a], zmm0</div>
<div><span style="white-space:pre-wrap"> </span>vmovdqu32<span style="white-space:pre-wrap"> </span>zmm0,
zmmword ptr [rip + c+64]</div>
<div><span style="white-space:pre-wrap"> </span>vpaddd<span style="white-space:pre-wrap"> </span>zmm0,
zmm0, zmmword ptr [rip + b+64]</div>
</div>
<div><br>
</div>
<div><br>
</div>
<div>and </div>
<div><br>
</div>
<div>eg. 2</div>
<div><br>
</div>
<div>
<div>mov<span style="white-space:pre-wrap"> </span>rax, -393216</div>
<div><span style="white-space:pre-wrap"> </span>.p2align<span style="white-space:pre-wrap"> </span>4,
0x90</div>
<div>.LBB0_1: # %vector.body</div>
<div> # =>This Inner
Loop Header: Depth=1</div>
<div><span style="white-space:pre-wrap"> </span><font color="#0000ff">vmovdqu32<span style="white-space:pre-wrap"> </span>zmm1,
zmmword ptr [rax + c+401344] ; load c[401344]
in zmm1</font></div>
<div><font color="#ff0000"><span style="white-space:pre-wrap"> </span>vmovdqu32<span style="white-space:pre-wrap"> </span>zmm0,
zmmword ptr [rax + c+401280] ;load b[401280]
in zmm0</font></div>
<div><font color="#0000ff"><span style="white-space:pre-wrap"> </span>vpaddd<span style="white-space:pre-wrap"> </span>zmm1,
zmm1, zmmword ptr [rax + b+401344] ;
zmm1<-zmm1+b[401344]</font></div>
<div><font color="#0000ff"><span style="white-space:pre-wrap"> </span>vmovdqu32<span style="white-space:pre-wrap"> </span>zmmword
ptr [rax + a+401344], zmm1 ; store zmm1 in
c[401344]</font></div>
</div>
<div>
<div><font color="#000000"><span style="white-space:pre-wrap"> </span>vmovdqu32<span style="white-space:pre-wrap"> </span>zmm1,
zmmword ptr [rax + c+401216]</font></div>
<div><font color="#ff0000"><span style="white-space:pre-wrap"> </span>vpaddd<span style="white-space:pre-wrap"> </span>zmm0,
zmm0, zmmword ptr [rax + b+401280] ;
zmm0<-zmm0+b[401280]</font></div>
<div><font color="#ff0000"><span style="white-space:pre-wrap"> </span>vmovdqu32<span style="white-space:pre-wrap"> </span>zmmword
ptr [rax + a+401280], zmm0 ; store zmm0 in
c[401280]</font></div>
<div><font color="#000000"><span style="white-space:pre-wrap"> </span>vmovdqu32<span style="white-space:pre-wrap"> </span>zmm0,
zmmword ptr [rax + c+401152]</font></div>
</div>
<div>........ in the remaining instructions also there is only
zmm0 and zmm1 used?</div>
<div><br>
</div>
<div>As you can see in the above examples there could be
multiple registers use. also i doubt if the above set of
repeating instructions in eg. 2 are executed in parallel? and
why repeat zmm0 and zmm1 cant it be more zmms and all in
parallel, mean the one w/o dependency. for eg in above example
blue has dependency in between and red has dependency among
each other they cant be executed in parallel but blue and red
can be executed in parallel?</div>
<div><br>
</div>
<div><br>
</div>
<div><br>
</div>
<div>Please correct me if I am wrong.</div>
<div><br>
</div>
<div><br>
</div>
</div>
<br>
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<br>
<pre class="m_-5033067552900698344m_-1589879501904212397m_7604358723266123794moz-signature" cols="72">--
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory</pre>
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