<html><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"></head><body><div>Hi,</div><div><br></div><div>Same here, my backend only has 64bit load/store. But i still use 64bit virt regs and expand/declare missing instructions by myself. </div><div><br></div><div>I'll try looking into sparc backend, thanks. Also, only after writing this post I found a bunch of built-in transforms. Still trying to understand how to use those.</div><div><br></div><div>By the way, constraint-wise (alignment), is there any difference between virt regclass and regtuple?</div><div><br></div><div>Best regards,</div><div>Petr</div><div><br></div><div><br></div><div><br></div><div id="composer_signature"><div style="font-size:85%;color:#575757" dir="auto">Отправлено со смартфона Samsung Galaxy.</div></div><div><br></div><div style="font-size:100%;color:#000000"><!-- originalMessage --><div>-------- Исходное сообщение --------</div><div>От: 陳韋任 <chenwj.cs97g@g2.nctu.edu.tw> </div><div>Дата: 16.06.17 22:03 (GMT+02:00) </div><div>Кому: tstellar@redhat.com </div><div>Копия: Peter Bel <upcfrost@gmail.com>, LLVM Developers Mailing List <llvm-dev@lists.llvm.org> </div><div>Тема: Re: [llvm-dev] Wide load/store optimization question </div><div><br></div></div><div dir="ltr"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">One thing you can do is define a register class that is made up of register<br>
tuples e.g. r0r1, r2r3, etc., and use that register class for the 64-bit<br>
load/store instructions. This will allow you to do the load/store<br>
merging before register allocation without the register constraints.</blockquote><div><br></div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif">Our backend only support load/store for i64 type, hence i64 is not legal for us.</div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif">I guess Peter's <span style="font-size:14px;font-family:arial,sans-serif">Epiphany arch</span> has similar situation.</div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif"><br></div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif">IIRC, LLVM expand load i64 to two load i32. Right now, we have to custom</div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif">lowering load i64 to load v2i32, then map v2i32 to the tuple register (similar</div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif">to Sparc backend). How can we use the tuple register for those two i32? </div></div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif">Any existing example?</div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif"><br></div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif">Regards,</div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif">chenwj</div><div><br></div>-- <br><div class="gmail_signature"><div dir="ltr"><div>Wei-Ren Chen (陳韋任)<br>Homepage: <a href="https://people.cs.nctu.edu.tw/~chenwj" target="_blank">https://people.cs.nctu.edu.tw/~chenwj</a></div></div></div>
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