<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jun 6, 2017 at 1:53 PM, Sreejita saha <span dir="ltr"><<a href="mailto:sreejitasaha2011@gmail.com" target="_blank">sreejitasaha2011@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr"><div><div><div><div><div><div><div>Hey, <br></div>So for doing such pointer arithmetic it doesn't load the values as the controller has no execution unit as such it does al computation in the memory itself.</div></div></div></div></div></div></div></blockquote><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr"><div><div><div><div><div><div></div>So for such a function it would do just an add which looks like this :<br>ADD @A, @B=<br>XOR @A,@B,@T; / / T = A xor B<br>AND @A,@B,@R; / / R = A · B<br>iRM 3w 0 , 1 ,@CI ; / / CI = 0<br>iRM 3w 0 , 1 ,@U; / / U = 0<br>iRM 3w 0 , 1 ,@V; / / V = 0<br>iRM 3w 1 ,@T,@U; / / U = T<br><br>iRM 3 @CI+0 ,@U+0 ,@V+ 1 ; / / V=[0, (c 0 · t 0 ), . . . , 0]<br>iRM 3 @R+ 0 , 0 , CI + 1 ; / / CI=[0, r 0 , . . . , 0]<br>iRM 3 @V+1,0,@CI+1; // CI=[0, (r 0 + (c 0 · t 0 )), . . . ]<br>..<br>.<br>iRM 3 @CI+62 @U+62 @V+ 6 3 ;<br>iRM 3 @R+ 6 2 , 0 ,@CI ;<br>iRM 3 @V+ 6 3 , 0 ,@CI+ 6 3 ;<br>XOR @T, @CI ,@A; / / A = A xor B xor CI<br><br></div>It doesnt print out the AND and XOR instructions , it performs them is a similar fashion, you can look up the AND I have written earlier,<br><br></div>The load is done:<br> iRM 3w 0 , 1 , Accum ;<br>L i + n : iRM 3w A, 1 , Accum ;<br><br></div>where the value of A is known at compile time from @A thats signified.</div></div></div></blockquote><div><br></div><div>So if I understand correctly, this ISA can only operate on statically known addresses in the memory array, correct? E.g. you could not walk a linked list.</div><div><br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr"><div><div> IRM 3w is basically a bitwise resistive majority done on an entire word(iRM 3) .</div></div></div></blockquote><div><br></div><div>To make sure I understand correctly, iRM 3w is equivalent to a sequence of 64 operations:</div><div><br></div><div>iRM 3w @A, @B, @C :=</div><div><br></div><div>iRM 3 @A+0, @B+0, @C+0</div><div>iRM 3 @A+1, @B+1, @C+1<br></div><div>...</div><div>iRM 3 @A+63, @B+63, @C+63<br></div><div><br></div><div>Is that correct?</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr"><div><div> Resistive majority is done as majority of A,B',C<br></div><div>It's quite complex<br></div>How do you think the instruction definition would work for such an architecture.<br></div></div></blockquote><div><br></div><div>You probably want to expand each input operation into equivalent instructions for your isa, as you have done in the example above. That will produce simple but correct code. You may want to write a follow-up peephole pass to do algebraic simplifications using identities of the resistive majority function.</div><div><br></div><div>You may want to watch <a href="https://www.youtube.com/watch?v=6tfb344A7w8">https://www.youtube.com/watch?v=6tfb344A7w8</a></div><div>You'll probably be able to identify places where the simplicity of your ISA makes certain parts trivial. E.g. in your case, there is only one "register bank" so that whole aspect of the lowering is trivialized. I haven't been keeping up to date with GlobalISel, so you might be better off using SelectionDAG. I'll let someone more familiar with the backend comment on that, but your target seems simple enough that even writing the backend from scratch (directly implementing TargetMachine like Matthias suggested) would be feasible. Hooking into LLVM's backend infrastructure seems like it will mostly just save you from writing a register allocator, so it might be worth doing just for that.</div><div><br></div><div>-- Sean Silva</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr"><div></div>Thanks<br></div><div class="gmail-HOEnZb"><div class="gmail-h5"><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Jun 5, 2017 at 6:26 PM, Sean Silva <span dir="ltr"><<a href="mailto:chisophugis@gmail.com" target="_blank">chisophugis@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote"><span>On Mon, Jun 5, 2017 at 1:45 PM, Sreejita saha <span dir="ltr"><<a href="mailto:sreejitasaha2011@gmail.com" target="_blank">sreejitasaha2011@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr">Hey Sean,<div>So the processor does in-memory computing, it reads instructions and operands from the memory array, performs the majority operations within the memory array itself.</div><div>It does instructions using resistive majority which is AB'+B'C+AC</div><div>Like it does AND operation as </div><div>1: 0, 1, @C; //C=0 </div><div>2: 0, 1, @Binv; //Binv=0 </div><div>3: 1, @B, @Binv; //Binv=B </div><div>4: @A, @Binv, @C; //C=A.B<br></div><div> where each operation is a resistive majority and operations are directly performed on the storage of C. It reads @A in a register , @B , reads A and B and directly writes into the memory @C. There are shift operators as well that are also performed in a similar way, loads, stores are also performed like this.</div></div></blockquote><div><br></div></span><div>Can you show an example of the load/store and add/shift? For example, how does your ISA represent this function?<br><br></div><div>void add(int *dst, int *src0, int *src1) {</div><div> *dst = *src0 + *src1;</div><div>}</div><span class="gmail-m_-1767282022382122002HOEnZb"><font color="#888888"><div><br></div><div>-- Sean Silva</div></font></span><div><div class="gmail-m_-1767282022382122002h5"><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr"><div> So I am trying to define this resistive majority instruction in my ISA.</div><div><br></div><div>Thanks!</div><span class="gmail-m_-1767282022382122002m_-2970721295627600085HOEnZb"><font color="#888888"><div>-Sreejita </div><div> <br></div></font></span></div><div class="gmail-m_-1767282022382122002m_-2970721295627600085HOEnZb"><div class="gmail-m_-1767282022382122002m_-2970721295627600085h5"><div class="gmail_extra"><br><div class="gmail_quote">On Sun, Jun 4, 2017 at 8:22 PM, Sean Silva <span dir="ltr"><<a href="mailto:chisophugis@gmail.com" target="_blank">chisophugis@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr">I'm having a hard time grasping what this ISA actually looks like.<div><br></div><div>When you say that it has a single instruction that is a majority function, I assume something like this:</div><div><br></div><div>MAJ rDst <- rSrc0, rSrc1, rSrc2</div><div>Semantics:</div><div>for (int i = 0; i < REGISTER_WIDTH; i++) {</div><div> rDst[i] = maj(rSrc0[i], rSrc1[i], rSrc2[i]);</div><div>}</div><div>Where maj(a, b, c) = (a & b) | (a & c) | (b & c)<br><div><br></div><div>But that doesn't make sense given your question.</div><div><br></div><div>MAJ is a bitwise operation, so how do you implement arithmetic instructions with it? You would need at least one other instruction (such as a bit shift) to establish dependency chains between bits.</div><div><br></div><div>Also, how do you decompose load/store into majority functions? It's not even clear to me what that would actually mean. You need to access the memory/IO bus somehow, and if your only instruction only reads/writes to registers, the only way to do that would be to have special registers that interface to the IO bus?</div><div><br></div><div>-- Sean Silva</div></div></div><div class="gmail_extra"><br><div class="gmail_quote"><div><div class="gmail-m_-1767282022382122002m_-2970721295627600085m_6209670664283932736h5">On Thu, Jun 1, 2017 at 8:13 PM, Sreejita saha via llvm-dev <span dir="ltr"><<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>></span> wrote:<br></div></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div><div class="gmail-m_-1767282022382122002m_-2970721295627600085m_6209670664283932736h5"><div lang="EN-US"><div class="gmail-m_-1767282022382122002m_-2970721295627600085m_6209670664283932736m_2012837813939142686m_8637115130387562025WordSection1"><p class="MsoNormal">Hello everyone,</p><p class="MsoNormal"><u></u> <u></u></p><p class="MsoNormal">I was trying to create an LLVM backend for a processor with a very simple architecture and that does all instructions like load, store, arithmetic and logical instructions using a bunch of majority functions. The processor has only one instruction(majority function) in its ISA and breaks down all other instructions into a number of majority instructions depending on what instruction it is. All the instructions have different combinations of majority operations. Is there any way to implement this without creating a new Selection DAG node for the majority operation?</p><p class="MsoNormal">I was thinking of creation of a new Selection DAG node and mapping all the other instructions like loads, stores as pseudo instructions and breaking them up. Can someone please help me with this?</p><p class="MsoNormal"><u></u> <u></u></p><p class="MsoNormal">Thanks!</p><p class="MsoNormal">Sreejita</p><p class="MsoNormal"><u></u> <u></u></p><p class="MsoNormal"><u></u> <u></u></p><p class="MsoNormal">Sent from <a href="https://go.microsoft.com/fwlink/?LinkId=550986" target="_blank">Mail</a> for Windows 10</p><p class="MsoNormal"><u></u> <u></u></p></div></div><br></div></div>______________________________<wbr>_________________<br>
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