<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Jun 5, 2017 at 1:45 PM, Sreejita saha <span dir="ltr"><<a href="mailto:sreejitasaha2011@gmail.com" target="_blank">sreejitasaha2011@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hey Sean,<div>So the processor does in-memory computing, it reads instructions and operands from the memory array, performs the majority operations within the memory array itself.</div><div>It does instructions using resistive majority which is AB'+B'C+AC</div><div>Like it does AND operation as </div><div>1: 0, 1, @C; //C=0 </div><div>2: 0, 1, @Binv; //Binv=0 </div><div>3: 1, @B, @Binv; //Binv=B </div><div>4: @A, @Binv, @C; //C=A.B<br></div><div> where each operation is a resistive majority and operations are directly performed on the storage of C. It reads @A in a register , @B , reads A and B and directly writes into the memory @C. There are shift operators as well that are also performed in a similar way, loads, stores are also performed like this.</div></div></blockquote><div><br></div><div>Can you show an example of the load/store and add/shift? For example, how does your ISA represent this function?<br><br></div><div>void add(int *dst, int *src0, int *src1) {</div><div> *dst = *src0 + *src1;</div><div>}</div><div><br></div><div>-- Sean Silva</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div> So I am trying to define this resistive majority instruction in my ISA.</div><div><br></div><div>Thanks!</div><span class="HOEnZb"><font color="#888888"><div>-Sreejita </div><div> <br></div></font></span></div><div class="HOEnZb"><div class="h5"><div class="gmail_extra"><br><div class="gmail_quote">On Sun, Jun 4, 2017 at 8:22 PM, Sean Silva <span dir="ltr"><<a href="mailto:chisophugis@gmail.com" target="_blank">chisophugis@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">I'm having a hard time grasping what this ISA actually looks like.<div><br></div><div>When you say that it has a single instruction that is a majority function, I assume something like this:</div><div><br></div><div>MAJ rDst <- rSrc0, rSrc1, rSrc2</div><div>Semantics:</div><div>for (int i = 0; i < REGISTER_WIDTH; i++) {</div><div> rDst[i] = maj(rSrc0[i], rSrc1[i], rSrc2[i]);</div><div>}</div><div>Where maj(a, b, c) = (a & b) | (a & c) | (b & c)<br><div><br></div><div>But that doesn't make sense given your question.</div><div><br></div><div>MAJ is a bitwise operation, so how do you implement arithmetic instructions with it? You would need at least one other instruction (such as a bit shift) to establish dependency chains between bits.</div><div><br></div><div>Also, how do you decompose load/store into majority functions? It's not even clear to me what that would actually mean. You need to access the memory/IO bus somehow, and if your only instruction only reads/writes to registers, the only way to do that would be to have special registers that interface to the IO bus?</div><div><br></div><div>-- Sean Silva</div></div></div><div class="gmail_extra"><br><div class="gmail_quote"><div><div class="m_6209670664283932736h5">On Thu, Jun 1, 2017 at 8:13 PM, Sreejita saha via llvm-dev <span dir="ltr"><<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>></span> wrote:<br></div></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div><div class="m_6209670664283932736h5"><div lang="EN-US" link="blue" vlink="#954F72"><div class="m_6209670664283932736m_2012837813939142686m_8637115130387562025WordSection1"><p class="MsoNormal">Hello everyone,</p><p class="MsoNormal"><u></u> <u></u></p><p class="MsoNormal">I was trying to create an LLVM backend for a processor with a very simple architecture and that does all instructions like load, store, arithmetic and logical instructions using a bunch of majority functions. The processor has only one instruction(majority function) in its ISA and breaks down all other instructions into a number of majority instructions depending on what instruction it is. All the instructions have different combinations of majority operations. Is there any way to implement this without creating a new Selection DAG node for the majority operation?</p><p class="MsoNormal">I was thinking of creation of a new Selection DAG node and mapping all the other instructions like loads, stores as pseudo instructions and breaking them up. Can someone please help me with this?</p><p class="MsoNormal"><u></u> <u></u></p><p class="MsoNormal">Thanks!</p><p class="MsoNormal">Sreejita</p><p class="MsoNormal"><u></u> <u></u></p><p class="MsoNormal"><u></u> <u></u></p><p class="MsoNormal">Sent from <a href="https://go.microsoft.com/fwlink/?LinkId=550986" target="_blank">Mail</a> for Windows 10</p><p class="MsoNormal"><u></u> <u></u></p></div></div><br></div></div>______________________________<wbr>_________________<br>
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