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<p class="MsoNormal">Hi folks,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I am developing backend for a new architecture, which has many Intrinsics with multiple outputs. However, I found TableGen doesn’t support such Intrinsics during Instruction Selection. <o:p></o:p></p>
<p class="MsoNormal">For example, load intrinsic with address updated.<o:p></o:p></p>
<p class="MsoNormal" style="line-height:11.25pt"><span style="font-size:9.0pt;font-family:Consolas;color:black">def int_xxx_load_addr_updated: Intrinsic<[llvm_i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>;<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">NVPTX has the same situation in the trunk, but it handles all intrinsics in source code which introduced a huge chunk of repetitive codes.
<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I have a patch for this issue, which is waiting for review.
<a href="https://reviews.llvm.org/D32280">https://reviews.llvm.org/D32280</a><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Any suggestions are highly appreciated.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Thanks,<o:p></o:p></p>
<p class="MsoNormal">Wenbo<o:p></o:p></p>
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