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<p>Hi Winter,</p>
<p><br>
</p>
<p>I'm not sure what went wrong then, maybe you missed adding these
flags somewhere.</p>
<p><br>
</p>
<p>I suggest taking a small test-case which has this behavior and
pushing it through llc with the -debug flag. That should show the
instruction graph after many of the selection and scheduling
stages. Check if the input graph of the scheduling stage indeed
now has the new flags register marked as a dependency between the
cmp and beq operations. That should also show the add and store
operations and hopefully demonstrate that the add operations are
now also marked as clobering the flags register.</p>
<p><br>
</p>
<p>Cheers,</p>
<p> Roel<br>
</p>
<br>
<div class="moz-cite-prefix">On 23-03-17 13:23, Liu winter wrote:<br>
</div>
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<p>Hi Roel,</p>
<p><br>
</p>
<p>Thanks a lot for your advice, I have added "Defs" and
"implicit" syntax of status register in the related
instructions. However, it seems that it couldn't take effect.
I would describe more details.</p>
<p><br>
</p>
<p>In my case, the "add" after "cmp" is used to calculate
address due to the <span>
limitation of addressing mode</span>, for example,</p>
<p><br>
</p>
<p><span>...</span></p>
<p><span>cmp r8, r9</span></p>
<p><span>add r14, sp, 19</span></p>
<p><span>store [r14], r7</span></p>
<p><span>add r14, sp, 18</span></p>
<p><span>store [r14], r6</span></p>
<p><span>beq LBB02</span></p>
<p><span>...</span></p>
<p><br>
</p>
<p>I have another try on AVR. The corresponding code is<br>
</p>
<p><br>
</p>
<p>...<br>
</p>
<p>cp r24, r18</p>
<p>cpc r25, r19</p>
<p>std Y+9, r18</p>
<p>std Y+10, r31<br>
</p>
<p>brne LBB0_1</p>
<p>rjmp LBB0_2<br>
</p>
<p>....</p>
<p><br>
</p>
<p>I haved added "Defs = [SREG]" and "(implicit SREG)" in the
definition of "std" instruction SDNode, i.e. "STDPtrQRr", but
nothing happened. I wonder
<br>
</p>
<p><br>
</p>
<p>1. if I forget some important steps.</p>
<p>2. or llvm couldn't deal with the case related to "store".</p>
<p><br>
</p>
<p>Yours,</p>
<p>winter<br>
</p>
<br>
<br>
<div style="color: rgb(0, 0, 0);">
<hr tabindex="-1" style="display:inline-block; width:98%">
<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt"
face="Calibri, sans-serif" color="#000000"><b>From:</b>
Roel Jordans <a class="moz-txt-link-rfc2396E" href="mailto:r.jordans@tue.nl"><r.jordans@tue.nl></a><br>
<b>Sent:</b> March 22, 2017 1:16<br>
<b>To:</b> Liu winter<br>
<b>Subject:</b> Re: [llvm-dev] Code selection problem in
LLVM backend</font>
<div> </div>
</div>
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<p>Hi,</p>
<p><br>
</p>
<p>You can define the status register in your register infor
and then mark all operations that define/use the status
register. For an example you can look at the AVR backend
which uses this technique.<br>
</p>
<p><br>
</p>
<p>Cheers,</p>
<p> Roel<br>
</p>
<br>
<div class="moz-cite-prefix">On 22-03-17 04:03, Liu winter
via llvm-dev wrote:<br>
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<p>Hi, <br>
</p>
<p><br>
</p>
<p>I'm currently writing a backend for a specific
platform. On the target platform, "add/sub" always
write a flag result. I used SDNode pattern "add/sub"
for these two instructions, however this leading to a
wrongly code as follows,</p>
<p><br>
cmp</p>
<p>...</p>
<p>add ...</p>
<p>...</p>
<p>beq</p>
<p><br>
</p>
<p>"add" changes the flag. Desired code is:</p>
<p><br>
</p>
<p>add...<br>
</p>
<p>cmp</p>
<p>... ;No add/sub</p>
<p>beq</p>
<p><br>
</p>
<p>Then I tried to use SDNode pattern "addc/subc"
instead, but it doesn't matter and cause some other
errors. What should I do to generate code that no
"add/sub" between "cmp" and "branch"?<br>
</p>
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