<div dir="ltr">Hello Madhur,<div><br></div><div>I meant any instructions that enable irregular accesses at the hardware level, e.g. a subset of Intel's AVX 512 and those <a href="https://software.intel.com/en-us/articles/understanding-gather-scatter-instructions-and-the-gather-scatter-unroll-compiler-switch">here</a>.</div><div><br></div><div>Thanks,</div><div>Sanjay</div><div><br></div><div class="gmail_quote"><div dir="ltr">On Mon, Feb 20, 2017 at 9:49 PM SANJAY SRIVALLABH SINGAPURAM <<a href="mailto:llvmresch_int01@iith.ac.in">llvmresch_int01@iith.ac.in</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr" class="gmail_msg">Hello !<div class="gmail_msg"><br class="gmail_msg"></div><div class="gmail_msg">Does the x86 back-end generate gather-scatter instructions for LLVM¬†gather-scatter¬†intrinsics ?</div><div class="gmail_msg"><br class="gmail_msg"></div><div class="gmail_msg">Also, do the NVPTX and AMDGPU back-ends generate equivalent instructions for GPUs ?</div><div class="gmail_msg"><br class="gmail_msg"></div><div class="gmail_msg">Thank You,</div><div class="gmail_msg">Sanjay</div></div></blockquote></div></div>