<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Feb 21, 2017, at 10:18 AM, Friedman, Eli via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">On 2/20/2017 7:15 PM, Alex Susu via llvm-dev wrote:</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px;" class=""> Hello.<br class=""> Does anybody have an idea why I'm getting the error below when using llc with arguments -O1 -disable-cgp? Note that this error is not given when using llc -O0. (I'd like to mention also I'm using custom Instruction selection for BUILD_VECTOR, which gets converted in my back end's machine instrution VLOAD_D, although the custom code seems to always select instructions in a valid way.)<br class=""><br class=""> ******** Pre-regalloc Machine LICM: Test ********<br class=""> Entering BB#4<br class=""> Hoist non-reg-pressure: %vreg50<def> = VLOAD_D 1; MSA128D:%vreg50 dbg:IfVectorize.c:37:16<br class=""> Hoisting %vreg50<def> = VLOAD_D 1; MSA128D:%vreg50 dbg:IfVectorize.c:37:16<br class=""> from BB#4 to BB#3<br class=""> Hoist non-reg-pressure: %vreg51<def> = VLOAD_D 0; MSA128D:%vreg51<br class=""> Hoisting %vreg51<def> = VLOAD_D 0; MSA128D:%vreg51<br class=""> from BB#4 to BB#3<br class=""> Can't remat / high reg-pressure: %vreg54<def> = COPY %vreg50; BoolMask:%vreg54 MSA128D:%vreg50 dbg:IfVectorize.c:37:16<br class=""> Can't remat / high reg-pressure: %vreg57<def> = COPY %vreg50; BoolMask:%vreg57 MSA128D:%vreg50 dbg:IfVectorize.c:37:16<br class=""> Entering BB#15<br class=""> Hoisting %vreg66<def> = LD_imm64 4294967296; GPR:%vreg66<br class=""> from BB#15 to BB#6<br class=""> Entering BB#12<br class=""> Hoist non-reg-pressure: %vreg83<def> = VLOAD_D 3; MSA128D:%vreg83 dbg:IfVectorize.c:42:13<br class=""> Hoisting %vreg83<def> = VLOAD_D 3; MSA128D:%vreg83 dbg:IfVectorize.c:42:13<br class=""> from BB#12 to BB#11<br class=""> Hoist non-reg-pressure: %vreg84<def> = ORV_D %vreg83, %vreg83; MSA128D:%vreg84,%vreg83,%vreg83 dbg:IfVectorize.c:42:18<br class=""> Hoisting %vreg84<def> = ORV_D %vreg83, %vreg83; MSA128D:%vreg84,%vreg83,%vreg83 dbg:IfVectorize.c:42:18<br class=""> from BB#12 to BB#11<br class=""> Hoist non-reg-pressure: %vreg86<def> = VLOAD_D 1; MSA128D:%vreg86 dbg:IfVectorize.c:42:13<br class=""> Hoisting %vreg86<def> = VLOAD_D 1; MSA128D:%vreg86 dbg:IfVectorize.c:42:13<br class=""> from BB#12 to BB#11<br class=""> Hoist non-reg-pressure: %vreg87<def> = VLOAD_D 0; MSA128D:%vreg87 dbg:IfVectorize.c:42:18<br class=""> Hoisting %vreg87<def> = VLOAD_D 0; MSA128D:%vreg87 dbg:IfVectorize.c:42:18<br class=""> from BB#12 to BB#11<br class=""> Hoist non-reg-pressure: %vreg85<def> = VLOAD_D 101; MSA128D:%vreg85 dbg:IfVectorize.c:42:13<br class=""> Hoisting %vreg85<def> = VLOAD_D 101; MSA128D:%vreg85 dbg:IfVectorize.c:42:13<br class=""> from BB#12 to BB#11<br class=""> Hoist non-reg-pressure: %vreg84<def> = ORV_D %vreg85, %vreg85; MSA128D:%vreg84,%vreg85,%vreg85 dbg:IfVectorize.c:42:18<br class=""> Hoisting %vreg84<def> = ORV_D %vreg85, %vreg85; MSA128D:%vreg84,%vreg85,%vreg85 dbg:IfVectorize.c:42:18<br class=""> from BB#12 to BB#11<br class=""> Can't remat / high reg-pressure: %vreg94<def> = COPY %vreg86; BoolMask:%vreg94 MSA128D:%vreg86 dbg:IfVectorize.c:42:13<br class=""><br class=""> llc: /llvm/lib/CodeGen/MachineRegisterInfo.cpp:339: llvm::MachineInstr* llvm::MachineRegisterInfo::getVRegDef(unsigned int) const: Assertion `(I.atEnd() || std::next(I) == def_instr_end()) && "getVRegDef assumes a single definition or no definition"' failed.<br class=""></blockquote><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">The immediate explanation of what this means if pretty easy: virtual registers are SSA (like values in LLVM IR), so every virtual register should have exactly one definition.</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""></div></blockquote><div>Just to be more exact here:</div><div><br class=""></div><div>virtual registers must be in SSA form as long as MachineRegisterInfo::isSSA() says so. In practice the PhiElimination and the TwoAddressInstruction passes destruct SSA form and clear this flag. Afterwards virtual registers may have multiple definitions (for example to model two address instructions or to have copies in multiple predecessor block where we had a phi before).</div><div><br class=""></div><div>Note though that even when the program is not in SSA form anymore we have some rules that vreg liveness must be continuos/connected. So a sequence of 4 instructions like "v0 = def; use v0; v0 = def; use v0" would be invalid as it would produce two disconnected live intervals which means that we could trivially rename half of the uses in the example to something like v1 and remove an unnecessary constraint on the register allocator.</div><div><br class=""></div><div>- Matthias</div><br class=""><blockquote type="cite" class=""><div class=""><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">You might want to try the "-verify-machineinstrs" flag to llc to get better error messages for mistakes like this.</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">-Eli</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; 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