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</o:shapelayout></xml><![endif]--></head><body lang=EN-IE link="#0563C1" vlink="#954F72"><div class=WordSection1><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;mso-fareast-language:EN-US'>Actually, we didn’t do this in any new transform pass, though we do custom lowering for many operations (e.g. shuffle); but the majority of the descriptions are in normal TableGen files. This goes though the usual LLVM instruction selection as chains of dependent instructions. The only other critical thing was to use ‘</span><span style='font-family:"Courier New";mso-fareast-language:EN-US'>setOperationAction</span><span style='font-family:"Book Antiqua",serif;mso-fareast-language:EN-US'>’ to select ‘</span><span style='font-family:"Courier New";mso-fareast-language:EN-US'>Expand</span><span style='font-family:"Book Antiqua",serif;mso-fareast-language:EN-US'>’, ‘</span><span style='font-family:"Courier New";mso-fareast-language:EN-US'>Legal</span><span style='font-family:"Book Antiqua",serif;mso-fareast-language:EN-US'> ‘and ‘</span><span style='font-family:"Courier New";mso-fareast-language:EN-US'>Custom</span><span style='font-family:"Book Antiqua",serif;mso-fareast-language:EN-US'>’ as appropriate to the instruction set.<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;mso-fareast-language:EN-US'>Pre-RA scheduling simply insures that appropriate schedules are correct for each chain, and the Post-RA scheduler then lays each chain down (bottom up in our model) and creates the bundles representing the VLIW instruction.<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;mso-fareast-language:EN-US'>The Hexagon target is a nice example of an in-tree target that does this.<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;mso-fareast-language:EN-US'> MartinO<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><b><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri",sans-serif'>From:</span></b><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri",sans-serif'> yangzhh@mail.ustc.edu.cn [mailto:yangzhh@mail.ustc.edu.cn] <br><b>Sent:</b> 20 February 2017 13:31<br><b>To:</b> Martin J. O'Riordan <martin.oriordan@movidius.com><br><b>Cc:</b> 'LLVM Developers' <llvm-dev@lists.llvm.org><br><b>Subject:</b> Re: RE: [llvm-dev] vectorization and vliw(very long instruction word)<o:p></o:p></span></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Thanks, I will modify some transform pass, because my specific target processor. I don't think this a good way, but I think this a easier way. Could I do that? <o:p></o:p></p><p><span style='font-family:"Calibri",sans-serif'>在</span>2017-02-20 20:47:36<span style='font-family:"Calibri",sans-serif'>，</span>Martin J. O'Riordan<a href="mailto:martin.oriordan@movidius.com">martin.oriordan@movidius.com</a><span style='font-family:"Calibri",sans-serif'>写道：</span><o:p></o:p></p><blockquote style='border:none;border-left:solid #CCCCCC 1.0pt;padding:0cm 0cm 0cm 6.0pt;margin-left:4.8pt;margin-right:0cm' name=replyContent><div><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;mso-fareast-language:EN-US'>Our approach is to let instruction selection and vectorisation happen as if the instruction set was single-issue, and use the post-RA scheduler to fill the VLIW slots with instructions from each of the functional-units [FUs] on a first-come, first-served basis. This works quite well in conjunction with some mutation patterns that allow an instruction from an alternative FU to be substituted if the preferred FU is busy.</span><o:p></o:p></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;mso-fareast-language:EN-US'> </span><o:p></o:p></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;mso-fareast-language:EN-US'>The VLWI nature of the target and the instruction selection and vectorisation are largely orthogonal. There are scheduling, register allocation and instruction selection decisions that an expert human programmer might do differently, but overall the compiler still produces solutions that are competitive with the solutions determined by expert assembly programmers.</span><o:p></o:p></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;mso-fareast-language:EN-US'> </span><o:p></o:p></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;mso-fareast-language:EN-US'> MartinO</span><o:p></o:p></p><p class=MsoNormal><span style='font-family:"Book Antiqua",serif;mso-fareast-language:EN-US'> </span><o:p></o:p></p><p class=MsoNormal><b><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri",sans-serif'>From:</span></b><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri",sans-serif'> llvm-dev [mailto:<a href="mailto:llvm-dev-bounces@lists.llvm.org">llvm-dev-bounces@lists.llvm.org</a>] <b>On Behalf Of </b>via llvm-dev<br><b>Sent:</b> 20 February 2017 02:37<br><b>To:</b> <a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a><br><b>Subject:</b> [llvm-dev] vectorization and vliw(very long instruction word)</span><o:p></o:p></p><p class=MsoNormal> <o:p></o:p></p><pre style='background:white'><span style='font-size:10.5pt'>Hello, I want to implement vectorization and vliw(very long instruction word) in my specific dsp ,do you have any advices to me ? </span><o:p></o:p></pre><pre style='background:white'><span style='font-size:10.5pt'>Thank you very much!</span><o:p></o:p></pre></div></blockquote></div></body></html>