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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Actually the K registers are currently represented by vectors of i1, except for the VK1 register class which is used with scalar i1 – that is the only one I intend
to change (to be a vector of i1 as well). <o:p></o:p></span></p>
<p class="MsoNormal"><a name="_MailEndCompose"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></a></p>
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<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> mehdi.amini@apple.com [mailto:mehdi.amini@apple.com]
<br>
<b>Sent:</b> Thursday, February 02, 2017 20:50<br>
<b>To:</b> Blank, Guy <guy.blank@intel.com><br>
<b>Cc:</b> llvm-dev@lists.llvm.org<br>
<b>Subject:</b> Re: [llvm-dev] [X86][AVX512] RFC: make i1 illegal in the Codegen<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On Jan 24, 2017, at 3:54 AM, Blank, Guy via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">Hi All,</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">AVX-512 introduced the K mask registers and masked operations which make a natural choice for legalizing vectors of i1’s.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">For example,<br>
<br>
<br>
</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">define <8 x i32> @foo(<8 x i32>%a, <8 x i32*> %p) {</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> %r = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %p, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i32> undef)</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> ret 8 x i32>%r</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">}</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">Can be lowered to</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"># BB#0:</span><o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">kxnorw %k0, %k0, %k1</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">vpgatherqd (,%zmm1), %ymm0 {%k1}</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">retq</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">Legal vectors of i1’s require support for BUILD_VECTOR(i1, i1, .., i1), i1 EXTRACT_VEC_ELEMENT (…) and INSERT_VEC_ELEMENT(i1, …) , so making i1 legal seemed like a sensible
decision, and this is the current state in the top of trunk.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">However, making i1 legal affected instruction selection of scalar code as well. Currently, there are cases where operations producing or consuming i1’s are selected (sub-optimally)
to instructions that act on K-regs.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"><a href="https://llvm.org/bugs/show_bug.cgi?id=28650"><span style="color:#954F72">PR28650</span></a><span class="apple-converted-space"> </span>is an example showing that i1’s
live-in or live-out of basic-blocks are being selected to K register classes, even though we don’t want this to happen. This problem does not happen on subtargets without the AVX-512 feature enabled.<br>
The following is the AVX-512 code from the bug report:</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"># BB#0: # %entry</span><o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">testb $1, %dil</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">je .LBB0_1</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"># BB#2: # %if</span><o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">pushq %rax</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">callq bar</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> # kill: %AL<def> %AL<kill> %EAX<def></span><o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">andl $1, %eax</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">kmovw %eax, %k0</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">addq $8, %rsp</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">jmp .LBB0_3</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">.LBB0_1:</span><o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">kxnorw %k0, %k0, %k0</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">kshiftrw $15, %k0, %k0</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">.LBB0_3: # %else</span><o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">kmovw %k0, %eax</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> # kill: %AL<def> %AL<kill> %EAX<kill></span><o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">Retq</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">The kmov,kxnor,kshiftr instructions here are the instructions operating on K registers. These are undesirable in the purely scalar input code.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">Having a type that can be possibly legalized to two different register classes exposes a fundamental limitation of the current instruction selection framework, and that is
we cannot always make the right decision about live-in/live-out i1’s because we cannot see beyond the boundary of the current basic-block we are visiting. As a side-note, with GlobalISel this can be solved, since we see the entire use-def chain at the function
level.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">Our initial thought was to write a pass that will be run after ISel to correct bad selections. The pass would examine the use-def chains containing values that were selected
to K-regsiter classes, and, when profitable, re-assign the values to GPR register classes (and replace the producing/consuming instructions accordingly). But even with this fix-up pass, we would still be losing many ISel pattern-matching rules that will be
missed because the instruction set acting on GPR is richer than the instruction set acting on K-regs. For example, a test trying to match the sbb instruction:</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">define i32 @test2(i32 %x, i32 %y, i32 %res) nounwind uwtable readnone ssp {</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">entry:</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> %cmp = icmp ugt i32 %x, %y</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> %dec = sext i1 %cmp to i32</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> %dec.res = add nsw i32 %dec, %res</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> ret i32 %dec.res</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">}</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">Generates the following with AVX2:</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"># BB#0: # %entry</span><o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">cmpl %edi, %esi</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">sbbl $0, %edx</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">movl %edx, %eax</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">retq</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">While AVX512 produces:</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"># BB#0: # %entry</span><o:p></o:p></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">xorl %ecx, %ecx</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">cmpl %esi, %edi</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">movl $-1, %eax</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">cmovbel %ecx, %eax</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">addl %edx, %eax</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">retq</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;margin-left:27.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">So we would still end-up with cases where when the AVX-512 feature is enabled, instruction selection for scalar code becomes inferior.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">Finally, we suggest to undo the above issues cause by legalizing i1, by making i1 illegal. This would make instruction selection of scalar code identical for both cases when
the AVX-512 feature is on and off. As for supporting BUILD_VECTOR, EXTRACT_VEC_ELEMENT and INSERT_VEC_ELEMENT, we believe we can support these operations even when i1 is illegal and the vectors of i1 *<b>are</b>* legal by using the i8 type instead of i1, as
it should be implicitly truncated/extended to the element type of the vNi1 vectors.<span class="apple-converted-space"> </span></span><o:p></o:p></p>
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</blockquote>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">FWIW this makes sense to me: using vector of i8 to represent the boolean values and making sure to select the right pattern to use the K register seems reasonable.<o:p></o:p></p>
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<p class="MsoNormal">How are you planning to implement the selection?<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Thanks,<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">— <o:p></o:p></p>
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<p class="MsoNormal">Mehdi<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><br>
<br>
<o:p></o:p></p>
<blockquote style="margin-top:5.0pt;margin-bottom:5.0pt">
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">I am now working on a patch that will implement this approach.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">Would appreciate to get feedback and comments.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">Thanks,</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">Guy</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> </span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> <o:p></o:p></span></p>
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