<div dir="ltr"><div><div><div>Turns out this was being caused by our own pre-register allocation instruction scheduler. The debug information caused calls to <span style="font-family:monospace,monospace">LiveIntervals::handleMove</span> to be ordered slightly differently. This change meant a range of slot indexes had to be renumbered.<br><br></div>I'm curious though. Despite the order of instructions being identical in both cases, the weights assigned to virtual registers was changed by the different slot indexes. Why does the register allocator use the absolute values of the slot indexes in this way when they don't seem to correspond directly to the structure of the incoming code?<br><br></div>Thanks,<br></div>Stephen<br></div><div class="gmail_extra"><br><div class="gmail_quote">On 2 February 2017 at 17:03, Robinson, Paul via llvm-dev <span dir="ltr"><<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">I remember running into cases where –g introduces pseudo-instructions for .cfi-* directives, and these become scheduling barriers and therefore affect the final
code a bit; I don't remember anything about register allocation being affected, though.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">A reproducer would be awesome.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">--paulr<u></u><u></u></span></p>
<p class="MsoNormal"><a name="m_680020821152319458__MailEndCompose"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></a></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> llvm-dev [mailto:<a href="mailto:llvm-dev-bounces@lists.llvm.org" target="_blank">llvm-dev-bounces@<wbr>lists.llvm.org</a>]
<b>On Behalf Of </b>Adrian Prantl via llvm-dev<br>
<b>Sent:</b> Thursday, February 02, 2017 8:46 AM<br>
<b>To:</b> David Blaikie<br>
<b>Cc:</b> <a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a><br>
<b>Subject:</b> Re: [llvm-dev] Register allocator behaves differently when compiling with and without -g<u></u><u></u></span></p>
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<p class="MsoNormal">On Feb 2, 2017, at 8:20 AM, David Blaikie <<a href="mailto:dblaikie@gmail.com" target="_blank">dblaikie@gmail.com</a>> wrote:<u></u><u></u></p>
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<p class="MsoNormal">The goal/intent is that debug info does not affect code generation. There are (many?) bugs. I think Apple folks (cc'd Adrian) may be looking at this a bit recently, not sure.<br>
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The fixes aren't usually too invasive (usually involve something counting instructions where it needs to skip counting debug intrinsics), if you're interested in having a go at fixing it yourself & sending a patch for review.<u></u><u></u></p>
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<p class="MsoNormal">Just wanted to add, if you are not able to fix it yourself, it would also be helpful if you could file a PR with a testcase.<u></u><u></u></p>
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<p class="MsoNormal">-- adrian<u></u><u></u></p>
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<p class="MsoNormal">On Thu, Feb 2, 2017 at 8:18 AM Stephen Rogers via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>> wrote:<u></u><u></u></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt">Hi all,<u></u><u></u></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt">In several of our tests, I have noticed that the register allocator allocates to virtual registers in a different order when compiling with the clang option -g. Before entering the register allocator, the code
is identical when compiling with and without -g (with the exception of "<span class="m_680020821152319458gmailmsg"><span style="font-family:"Courier New"">DBG_VALUE</span></span>" instructions). The only difference I can see is the value assigned to the slot index for each instruction.
As an example, without -g a snippet of a basic block looks like this:<br>
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<span class="m_680020821152319458gmailmsg">32B %vreg29<def> = LDImm 1; REG1:%vreg29</span><br>
<span class="m_680020821152319458gmailmsg">36B %vreg44<def> = LDImm 1103515245; REG1:%vreg44</span><br>
<span class="m_680020821152319458gmailmsg">40B %vreg143:vsub32_1<def,read-<wbr>undef> = LDImm 0; REG2:%vreg143</span><br>
<span class="m_680020821152319458gmailmsg">44B %vreg68<def> = LDImm 12345; REG1:%vreg68</span><br>
<span class="m_680020821152319458gmailmsg">64B %vreg143:vsub32_0<def> = COPY %vreg143:vsub32_1; REG2:%vreg143</span><br>
<span class="m_680020821152319458gmailmsg">72B %vreg78<def> = LDImm 32; REG1:%vreg78</span></span><u></u><u></u></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><span class="m_680020821152319458gmailmsg"><span style="font-family:"Arial","sans-serif"">But when I specify -g, this becomes:</span></span><span style="font-family:"Arial","sans-serif""><br>
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</span><span class="m_680020821152319458gmailmsg"><span style="font-family:"Courier New"">32B %vreg29<def> = LDImm 1; REG1:%vreg29 dbg:path/to/source:9:34 @[ path/to/source:25:13 ]</span></span><span style="font-family:"Courier New""><br>
<span class="m_680020821152319458gmailmsg">36B %vreg44<def> = LDImm 1103515245; REG1:%vreg44 dbg:path/to/source:9:34 @[ path/to/source:25:13 ]</span><br>
<span class="m_680020821152319458gmailmsg"><span style="color:red;background:white">44B</span> %vreg143:vsub32_1<def,read-<wbr>undef> = LDImm 0; REG2:%vreg143</span><br>
<span class="m_680020821152319458gmailmsg"><span style="color:red">48B</span> %vreg68<def> = LDImm 12345; REG1:%vreg68 dbg:path/to/source:9:47 @[ path/to/source:25:13 ]</span><br>
<span class="m_680020821152319458gmailmsg"><span style="color:red">56B</span> %vreg143:vsub32_0<def> = COPY %vreg143:vsub32_1; REG2:%vreg143</span><br>
<span class="m_680020821152319458gmailmsg"><span style="color:red">60B</span> %vreg78<def> = LDImm 32; REG1:%vreg78</span></span><u></u><u></u></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><span class="m_680020821152319458gmailmsg"><span style="font-family:"Arial","sans-serif"">This change seems to affect the weight assigned to the
</span></span><span class="m_680020821152319458gmailmsg"><span style="font-family:"Courier New"">LiveIntervals</span></span><span class="m_680020821152319458gmailmsg"><span style="font-family:"Arial","sans-serif""> for each virtual register which in turn changes the allocation order.</span></span><u></u><u></u></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><span class="m_680020821152319458gmailmsg"><span style="font-family:"Arial","sans-serif"">It would be my expectation that LLVM should generate identical code for a source file with and without debug information enabled. Is it possible
we are missing some hook in our target backend that would prevent this? Or is this the expected behaviour in LLVM?</span></span><u></u><u></u></p>
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<p class="MsoNormal"><span class="m_680020821152319458gmailmsg"><span style="font-family:"Arial","sans-serif"">Thanks,</span></span><u></u><u></u></p>
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<p class="MsoNormal"><span class="m_680020821152319458gmailmsg"><span style="font-family:"Arial","sans-serif"">Stephen</span></span><u></u><u></u></p>
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