<div dir="ltr">test/MC/X86 goes thorugh the AsmParser. That's a different path than isel. I'm worried about not being able to see cases where isel is missing a pattern and causes us to still select a VEX instruction. I've fixed many such cases recently and I'm sure there are still more. Since simple tests don't use the larger register set, the encoding is the only way we can tell what isel is doing.</div><div class="gmail_extra"><br clear="all"><div><div class="gmail_signature" data-smartmail="gmail_signature">~Craig</div></div>
<br><div class="gmail_quote">On Thu, Nov 24, 2016 at 12:20 AM, Demikhovsky, Elena <span dir="ltr"><<a href="mailto:elena.demikhovsky@intel.com" target="_blank">elena.demikhovsky@intel.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
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<p class="MsoNormal"><a name="m_-8968112922576746484__MailEndCompose">> I would like a command line option to disable this optimization. That way tests can still verify that EVEX instructions came out of isel by using -show-mc-encoding.<u></u><u></u></a></p>
<p class="MsoNormal"><u></u> <u></u></p>
</span><p class="MsoNormal">I think that keeping tests compatibility is not a reason for an additional “llc” flag. We check encoding in test/MC/X86 dir.<u></u><u></u></p>
<p class="MsoNormal">Is there any option to report-out from llc in non-debug mode? It should be an option to control internals of llc process..<u></u><u></u></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
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<p class="MsoNormal" style="margin-left:36.0pt">
<u></u><span style="font-family:"Calibri",sans-serif;color:#2f5496"><span>-<span style="font:7.0pt "Times New Roman"">
</span></span></span><u></u><span dir="LTR"></span><b><i><span style="color:#2f5496"> Elena<u></u><u></u></span></i></b></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
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<p class="MsoNormal"><a name="m_-8968112922576746484______replyseparator"></a><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Haber, Gadi
<br>
<b>Sent:</b> Thursday, November 24, 2016 09:28<br>
<b>To:</b> Craig Topper <<a href="mailto:craig.topper@gmail.com" target="_blank">craig.topper@gmail.com</a>>; Hal Finkel <<a href="mailto:hfinkel@anl.gov" target="_blank">hfinkel@anl.gov</a>><br>
<b>Cc:</b> <a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>; Demikhovsky, Elena <<a href="mailto:elena.demikhovsky@intel.com" target="_blank">elena.demikhovsky@intel.com</a>>; Rackover, Zvi <<a href="mailto:zvi.rackover@intel.com" target="_blank">zvi.rackover@intel.com</a>><br>
<b>Subject:</b> RE: [llvm-dev] RFC: code size reduction in X86 by replacing EVEX with VEX encoding<u></u><u></u></span></p>
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<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Thanx. This makes sense.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Note that there are many tests, mostly under test/CodeGen/X86, that are affected by this optimization and I had to modify them as they include a check of the
generated encoding.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">If we add such a disabling opt flag, should we now keep two sets of tests? One for the optimization on and one when it is disabled?<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal" style="margin-bottom:12.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Thanx!<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Gadi.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Craig Topper [<a href="mailto:craig.topper@gmail.com" target="_blank">mailto:craig.topper@gmail.com</a><wbr>]
<br>
<b>Sent:</b> Wednesday, November 23, 2016 18:13<br>
<b>To:</b> Haber, Gadi <<a href="mailto:gadi.haber@intel.com" target="_blank">gadi.haber@intel.com</a>>; Hal Finkel <<a href="mailto:hfinkel@anl.gov" target="_blank">hfinkel@anl.gov</a>><br>
<b>Cc:</b> <a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a><br>
<b>Subject:</b> Re: [llvm-dev] RFC: code size reduction in X86 by replacing EVEX with VEX encoding<u></u><u></u></span></p>
<p class="MsoNormal"><u></u> <u></u></p>
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<p class="MsoNormal">I would like a command line option to disable this optimization. That way tests can still verify that EVEX instructions came out of isel by using -show-mc-encoding.<u></u><u></u></p>
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<p class="MsoNormal"><u></u> <u></u></p>
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<p class="MsoNormal">On Wed, Nov 23, 2016 at 5:01 AM Hal Finkel via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>> wrote:<u></u><u></u></p>
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<p class="MsoNormal"><b><span style="font-family:"Helvetica",sans-serif;color:black">From:
</span></b><span style="font-family:"Helvetica",sans-serif;color:black">"Gadi via llvm-dev Haber" <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>><br>
<b>To: </b><a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a><br>
<b>Sent: </b>Wednesday, November 23, 2016 5:50:42 AM<br>
<b>Subject: </b>[llvm-dev] RFC: code size reduction in X86 by replacing EVEX with VEX encoding<u></u><u></u></span></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><span style="font-family:"Helvetica",sans-serif;color:black"><u></u> <u></u></span></p>
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<p class="MsoNormal"><span style="color:black">Hi All.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black"> <u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black">This is an RFC for a proposed target specific X86 optimization for reducing code size in the encoding of AVX-512 instructions when possible.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black"> <u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black">When the AVX512F instruction set was introduced in X86 it included additional 32 registers of 512bit size each ZMM0 - ZMM31, as well as additional 16 XMM
registers XMM16-XMM31 and 16 YMM registers YMM16-YMM31.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black">In order to encode the new registers of 16-31 and the additional instructions, a new encoding prefix called EVEX</span><span class="m_-8968112922576746484gmailmsg"><span style="color:#1f497d">,</span></span><span style="color:black">
which extends the existing VEX encoding</span><span class="m_-8968112922576746484gmailmsg"><span style="color:#1f497d">,</span></span><span style="color:black"> was introduced as shown below:<u></u><u></u></span></p>
<p class="MsoNormal"><span class="m_-8968112922576746484gmailmsg"><span style="color:#1f497d"> </span></span><span style="color:black"><u></u><u></u></span></p>
<p class="MsoNormal"><span class="m_-8968112922576746484gmailmsg"><span style="font-size:9.5pt;font-family:Consolas;color:black">The EVEX encoding format:</span></span><span style="color:black"><u></u><u></u></span></p>
<p class="MsoNormal"><span class="m_-8968112922576746484gmailmsg"><span style="font-size:9.5pt;font-family:Consolas;color:black"> EVEX Opcode ModR/M [SIB] [Disp32] / [Disp8*N] [Immediate]</span></span><span style="color:black"><u></u><u></u></span></p>
<p class="MsoNormal"><span class="m_-8968112922576746484gmailmsg"><span style="font-size:9.5pt;font-family:Consolas;color:black"># of bytes: 4 1 1 1 4 / 1 1</span></span><span style="color:black"><u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black"> <u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black">The existing VEX encoding format:<u></u><u></u></span></p>
<p class="MsoNormal"><span class="m_-8968112922576746484gmailmsg"><span style="font-size:9.5pt;font-family:Consolas;color:black"> [VEX] OPCODE ModR/M [SIB] [DISP] [IMM]</span></span><span style="color:black"><u></u><u></u></span></p>
<p class="MsoNormal"><span class="m_-8968112922576746484gmailmsg"><span style="font-size:9.5pt;font-family:Consolas;color:black"># of bytes: 0,2,3 1 1 0,1 0,1,2,4 0,1</span></span><span style="color:black"><u></u><u></u></span></p>
<p class="MsoNormal"><span class="m_-8968112922576746484gmailmsg"><span style="font-size:9.5pt;font-family:Consolas;color:green"> </span></span><span style="color:black"><u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black">Note that the EVEX prefix requires 4 bytes whereas the VEX prefix can take only up to 3 bytes.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black">Consequently, for the SKX architecture, many instructions that use only the lower registers of XMM0-XMM15 or YMM0-YMM15, can be encoded by either the EVEX
or the VEX format. For such cases, using the VEX encoding results in a code size reduction of ~2 bytes even though it is compiled with the AVX512F/AVX512VL features enabled.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black"> <u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black">For example: “vmovss %xmm0, 32(%rsp,%rax,4)“, has the following 2 possible encodings:<u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black"> <u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black">EVEX encoding (8 bytes long):<u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black"> 62 f1 7e 08 11 44 84 08 vmovss %xmm0, 32(%rsp,%rax,4)<u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black"> <u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black">VEX encoding (6 bytes long):<u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black"> c5 fa 11 44 84 20 vmovss %xmm0, 32(%rsp,%rax,4)<u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black"> <u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black">See reported Bugzilla bugs about this proposed optimization:<u></u><u></u></span></p>
<p class="MsoNormal"><span class="m_-8968112922576746484gmailmsg"><span style="color:#1f497d"><a href="https://llvm.org/bugs/show_bug.cgi?id=23376" target="_blank">https://llvm.org/bugs/show_<wbr>bug.cgi?id=23376</a></span></span><span style="color:black"><u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black"><a href="https://llvm.org/bugs/show_bug.cgi?id=29162" target="_blank">https://llvm.org/bugs/show_<wbr>bug.cgi?id=29162</a><u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black"> <u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black">The proposed optimization implementation is to add a table of all EVEX opcodes that can be encoded via VEX in a new header file placed under lib/Target/X86.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black">A new pass is to be added at the pre-emit stage</span><span class="m_-8968112922576746484gmailmsg"><span style="color:#1f497d">.</span></span><span style="color:black"><u></u><u></u></span></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:black">It might be better to have TableGen generate the mapping table for you instead of manually making a table yourself. TableGen has a feature that is specifically designed
to make mapping tables like this. For examples, grep for InstrMapping in:<br>
<br>
lib/Target/Hexagon/Hexagon.td<br>
lib/Target/Mips/<wbr>MipsDSPInstrFormats.td<br>
lib/Target/Mips/<wbr>MipsInstrFormats.td<br>
lib/Target/Mips/<wbr>Mips32r6InstrFormats.td<br>
lib/Target/PowerPC/PPC.td<br>
lib/Target/AMDGPU/SIInstrInfo.<wbr>td<br>
lib/Target/AMDGPU/<wbr>R600Instructions.td<br>
lib/Target/SystemZ/<wbr>SystemZInstrFormats.td<br>
lib/Target/Lanai/<wbr>LanaiInstrInfo.td<br>
<br>
I've used this feature a few times in the PowerPC backend, and it's quite convenient.<br>
<br>
-Hal<u></u><u></u></span></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:black"><u></u> <u></u></span></p>
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<p class="MsoNormal"><span style="color:black">No need for special Opt flags, as it is always better to use the reduced VEX encoding when possible.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black"> <u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black">Thank you for any comments or questions that you may have.<u></u><u></u></span></p>
<p class="MsoNormal"><span class="m_-8968112922576746484gmailmsg"><span style="color:#1f497d"> </span></span><span style="color:black"><u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black">Sincerely,
<u></u><u></u></span></p>
<p class="MsoNormal"><span class="m_-8968112922576746484gmailmsg"><span style="color:#1f497d"> </span></span><span style="color:black"><u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black">Gadi.
<u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:black"> <u></u><u></u></span></p>
</div>
<p class="m_-8968112922576746484gmailmsg1"><span style="font-family:"Helvetica",sans-serif;color:black">------------------------------<wbr>------------------------------<wbr>---------<br>
Intel Israel (74) Limited<u></u><u></u></span></p>
<p class="m_-8968112922576746484gmailmsg1"><span style="font-family:"Helvetica",sans-serif;color:black">This e-mail and any attachments may contain confidential material for<br>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:black">--
<u></u><u></u></span></p>
<div>
<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:black">Hal Finkel<br>
Lead, Compiler Technology and Programming Languages<br>
Leadership Computing Facility<br>
Argonne National Laboratory<u></u><u></u></span></p>
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