<html><head><style type='text/css'>p { margin: 0; }</style></head><body><div style='font-family: arial,helvetica,sans-serif; font-size: 10pt; color: #000000'><br><hr id="zwchr"><blockquote style="border-left: 2px solid rgb(16, 16, 255); margin-left: 5px; padding-left: 5px; color: rgb(0, 0, 0); font-weight: normal; font-style: normal; text-decoration: none; font-family: Helvetica,Arial,sans-serif; font-size: 12pt;"><b>From: </b>"Gadi via llvm-dev Haber" <llvm-dev@lists.llvm.org><br><b>To: </b>llvm-dev@lists.llvm.org<br><b>Sent: </b>Wednesday, November 23, 2016 5:50:42 AM<br><b>Subject: </b>[llvm-dev] RFC: code size reduction in X86 by replacing EVEX with VEX encoding<br><br>
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<p class="MsoNormal">Hi All.</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">This is an RFC for a proposed target specific X86 optimization for reducing code size in the encoding of AVX-512 instructions when possible.</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">When the AVX512F instruction set was introduced in X86 it included additional 32 registers of 512bit size each ZMM0 - ZMM31, as well as additional 16 XMM registers XMM16-XMM31 and 16 YMM registers YMM16-YMM31.</p>
<p class="MsoNormal">In order to encode the new registers of 16-31 and the additional instructions, a new encoding prefix called EVEX<span style="color: rgb(31, 73, 125);">,</span> which extends the existing VEX encoding<span style="color: rgb(31, 73, 125);">,</span> was introduced
as shown below:</p>
<p class="MsoNormal"><span style="color: rgb(31, 73, 125);"> </span></p>
<p class="MsoNormal" style=""><span style="font-size: 9.5pt; font-family: Consolas; color: black;">The EVEX encoding format:</span></p>
<p class="MsoNormal"><span style="font-size: 9.5pt; font-family: Consolas;"> EVEX Opcode ModR/M [SIB] [Disp32] / [Disp8*N] [Immediate]</span></p>
<p class="MsoNormal" style=""><span style="font-size: 9.5pt; font-family: Consolas;"># of bytes: 4 1 1 1 4 / 1 1</span></p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">The existing VEX encoding format:</p>
<p class="MsoNormal" style=""><span style="font-size: 9.5pt; font-family: Consolas;"> [VEX] OPCODE ModR/M [SIB] [DISP] [IMM]</span></p>
<p class="MsoNormal" style=""><span style="font-size: 9.5pt; font-family: Consolas;"># of bytes: 0,2,3 1 1 0,1 0,1,2,4 0,1</span></p>
<p class="MsoNormal" style=""><span style="font-size: 9.5pt; font-family: Consolas; color: green;"> </span></p>
<p class="MsoNormal">Note that the EVEX prefix requires 4 bytes whereas the VEX prefix can take only up to 3 bytes.</p>
<p class="MsoNormal">Consequently, for the SKX architecture, many instructions that use only the lower registers of XMM0-XMM15 or YMM0-YMM15, can be encoded by either the EVEX or the VEX format. For such cases, using the VEX encoding results in a code size
reduction of ~2 bytes even though it is compiled with the AVX512F/AVX512VL features enabled.</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">For example: “vmovss %xmm0, 32(%rsp,%rax,4)“, has the following 2 possible encodings:</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">EVEX encoding (8 bytes long):</p>
<p class="MsoNormal"> 62 f1 7e 08 11 44 84 08 vmovss %xmm0, 32(%rsp,%rax,4)</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">VEX encoding (6 bytes long):</p>
<p class="MsoNormal"> c5 fa 11 44 84 20 vmovss %xmm0, 32(%rsp,%rax,4)</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">See reported Bugzilla bugs about this proposed optimization:<span style="color: rgb(31, 73, 125);"></span></p>
<p class="MsoNormal"><span style="color: rgb(31, 73, 125);"><a href="https://llvm.org/bugs/show_bug.cgi?id=23376" target="_blank">https://llvm.org/bugs/show_bug.cgi?id=23376</a></span></p>
<p class="MsoNormal"><a href="https://llvm.org/bugs/show_bug.cgi?id=29162" target="_blank">https://llvm.org/bugs/show_bug.cgi?id=29162</a></p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">The proposed optimization implementation is to add a table of all EVEX opcodes that can be encoded via VEX in a new header file placed under lib/Target/X86.</p>
<p class="MsoNormal">A new pass is to be added at the pre-emit stage<span id="DWT257" style="color: rgb(31, 73, 125);">.</span></p></div></blockquote>It might be better to have TableGen generate the mapping table for you instead of manually making a table yourself. TableGen has a feature that is specifically designed to make mapping tables like this. For examples, grep for InstrMapping in:<br><br>lib/Target/Hexagon/Hexagon.td<br>lib/Target/Mips/MipsDSPInstrFormats.td<br>lib/Target/Mips/MipsInstrFormats.td<br>lib/Target/Mips/Mips32r6InstrFormats.td<br>lib/Target/PowerPC/PPC.td<br>lib/Target/AMDGPU/SIInstrInfo.td<br>lib/Target/AMDGPU/R600Instructions.td<br>lib/Target/SystemZ/SystemZInstrFormats.td<br>lib/Target/Lanai/LanaiInstrInfo.td<br><br>I've used this feature a few times in the PowerPC backend, and it's quite convenient.<br><br> -Hal<br><blockquote style="border-left: 2px solid rgb(16, 16, 255); margin-left: 5px; padding-left: 5px; color: rgb(0, 0, 0); font-weight: normal; font-style: normal; text-decoration: none; font-family: Helvetica,Arial,sans-serif; font-size: 12pt;"><div class="WordSection1"><p class="MsoNormal"><span style="color: rgb(31, 73, 125);"></span></p>
<p class="MsoNormal">No need for special Opt flags, as it is always better to use the reduced VEX encoding when possible.</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">Thank you for any comments or questions that you may have.</p>
<p class="MsoNormal"><span style="color: rgb(31, 73, 125);"> </span></p>
<p class="MsoNormal">Sincerely, </p>
<p class="MsoNormal"><span style="color: rgb(31, 73, 125);"> </span></p>
<p class="MsoNormal">Gadi. </p>
<p class="MsoNormal"> </p>
</div>
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