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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On 11/15/2016 4:22 PM, Pete Couperus via llvm-dev wrote:<span style="font-size:12.0pt"><o:p></o:p></span></p>
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<p class="MsoNormal">Hello,<o:p></o:p></p>
<p class="MsoNormal"> <o:p></o:p></p>
<p class="MsoNormal">Context: We have a backend where v32i1 is a Legal type, but the storage for v32i1 is not 32-bits/uses a different instruction sequence.<o:p></o:p></p>
<p class="MsoNormal">We ran into an issue because combineLoadToOperationType changed v32i1 loads into i32 loads, so a sequence like:<o:p></o:p></p>
<p class="MsoNormal">define void @bits(<32 x i1>* %A, <32 x i1>* %B) {<o:p></o:p></p>
<p class="MsoNormal"> %a = load <32 x i1>, <32 x i1>* %A<o:p></o:p></p>
<p class="MsoNormal"> store <32 x i1> %a, <32 x i1>* %B<o:p></o:p></p>
<p class="MsoNormal"> ret void<o:p></o:p></p>
<p class="MsoNormal">}<o:p></o:p></p>
<p class="MsoNormal"> <o:p></o:p></p>
<p class="MsoNormal">Is transformed to:<o:p></o:p></p>
<p class="MsoNormal">define void @bits(<32 x i1>* %A, <32 x i1>* %B) {<o:p></o:p></p>
<p class="MsoNormal"> %1 = bitcast <32 x i1>* %A to i32*<o:p></o:p></p>
<p class="MsoNormal"> %a1 = load i32, i32* %1, align 4<o:p></o:p></p>
<p class="MsoNormal"> %2 = bitcast <32 x i1>* %B to i32*<o:p></o:p></p>
<p class="MsoNormal"> store i32 %a1, i32* %2, align 4<o:p></o:p></p>
<p class="MsoNormal"> ret void<o:p></o:p></p>
<p class="MsoNormal">}<o:p></o:p></p>
<p class="MsoNormal"> <o:p></o:p></p>
<p class="MsoNormal">This looks to be intentional. <o:p></o:p></p>
<p class="MsoNormal">Is there a way to specify in the data-layout that v32i1 storage is not 32-bits?<o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Times New Roman",serif"><br>
No, not at the moment. You could propose something, but you'd probably have a hard time convincing anyone it's necessary; nobody has cared about this for a very long time.<br>
<br>
<br>
<o:p></o:p></span></p>
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<p class="MsoNormal">Absent that, is there any other reliable way to retain the original vector loads/store without just disabling this part of InstCombine?<o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Times New Roman",serif"><br>
No, and you'll run into other problems (e.g. alias analysis) if the data layout lies about the size of a load or store.<br>
<br>
<br>
<o:p></o:p></span></p>
<blockquote style="margin-top:5.0pt;margin-bottom:5.0pt">
<p class="MsoNormal">Or is it the backend’s responsibility to try and work with this?<o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"Times New Roman",serif"><br>
Where are these loads coming from? x86 without AVX512 doesn't have any convenient way generate code for a <32 x i1> store, but it doesn't matter because frontends don't generate <N x i1> loads and stores.<br>
<br>
If you have a frontend which is generating loads and stores like this, you could probably change it to use some other sequence (like a platform-specific intrinsic, or some sequence involving sext/trunc).<br>
<br>
<br>
<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:windowtext">We do have a frontend that can generate <32 x i1> loads/stores, though it is rare that these are inst-combined to i32 loads/stores like here (these were only illustrative examples).<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:windowtext">I’m trying to decide what the best way to remedy this is, and this info and suggestions help.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:windowtext">Thanks!<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:windowtext"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:windowtext">Pete<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:windowtext"><o:p> </o:p></span></p>
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