<p dir="ltr">Just a thought. What about putting a dummy barrier between the instructions during selectionDAG creation? </p>
<div class="gmail_extra"><br><div class="gmail_quote">On Nov 16, 2016 4:00 AM, "Ryan Taylor via llvm-dev" <<a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div>Setting the MI as isTerminator  should have the same impact, yes? I'm not sure of the other consequences of this though, if any, have to look into it.</div><div><br></div><div>Thanks.</div><div><br></div><div>-Ryan</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Nov 15, 2016 at 5:18 PM, Krzysztof Parzyszek <span dir="ltr"><<a href="mailto:kparzysz@codeaurora.org" target="_blank">kparzysz@codeaurora.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">You can override TargetInstrInfo::isSchedulingB<wbr>oundary for that.<br>
<br>
-Krzysztof<span><br>
<br>
On 11/15/2016 4:13 PM, Ryan Taylor wrote:<br>
</span><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;padding-left:1ex;border-left-color:rgb(204,204,204);border-left-width:1px;border-left-style:solid"><span>
I have the same issue, would it be easier and more useful to attach a<br>
flag to the instruction to tell the scheduler not to move instructions<br>
across this boundary?<br>
<br>
-Ryan<br>
<br>
On Tue, Nov 15, 2016 at 5:11 PM, Krzysztof Parzyszek via llvm-dev<br></span><div><div class="m_-7312215327072905670h5">
<<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a> <mailto:<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.or<wbr>g</a>>> wrote:<br>
<br>
    You can create a DAG mutation that adds artificial dependencies<br>
    between A, B and Z.<br>
<br>
    -Krzysztof<br>
<br>
<br>
    On 11/15/2016 3:26 PM, Wei Ding via llvm-dev wrote:<br>
<br>
        Hello,<br>
<br>
        I have a LLVM backend question regarding how to prevent compiler<br>
        from<br>
        reordering instructions. For example, I have the following<br>
        instructions.<br>
        Z_instruction is the one which I want to insert.<br>
<br>
<br>
        // instruction order which I am looking for<br>
        //////////////////////////////<wbr>///////////<br>
        A_instruction<br>
        B_instruction<br>
<br>
        *Z_instruction*<br>
<br>
        C_instruction<br>
        D_instruction<br>
        E_instruction<br>
        F_instruction<br>
<br>
        *Z_instruction*<br>
<br>
        G_instruction<br>
        F_instruction<br>
<br>
<br>
        ==============================<wbr>====================<br>
<br>
        But I found compiler reordered those instructions like the<br>
        following.<br>
        How could I prevent compiler from moving *A_instruction* and<br>
        *B_instruction* after the first *Z_instruction*? Any<br>
        recommendations and<br>
        suggestion are greatly appreciated here!!!<br>
<br>
        *Z_instruction*<br>
        *<br>
        *<br>
        A_instruction<br>
        B_instruction<br>
<br>
        C_instruction<br>
        D_instruction<br>
        E_instruction<br>
        F_instruction<br>
<br>
        *Z_instruction*<br>
<br>
        G_instruction<br>
        F_instruction<br>
<br>
        BTW, I have define input/output chain for : *C_instruction,<br>
        D_instruction, E_instruction, F_instruction and Z_instruction*<br>
        *<br>
        *<br>
        Thank you so much!<br>
<br>
        --<br>
        Wei Ding<br>
<br>
<br>
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