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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Hi Charith,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">After taking a quick look it seems we could do better for the 256-bit shuffles.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Can you please open a bug report (https://llvm.org/bugs, product=libraries, component=backend: X86) for this? It would be helpful if you minimized shuffle.ll
to say two functions. One function will perform the 128-bit shuffles and 256-bit shuffles in the second.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Thanks, Zvi<o:p></o:p></span></p>
<p class="MsoNormal"><a name="_MailEndCompose"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></a></p>
<p class="MsoNormal"><a name="_____replyseparator"></a><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> llvm-dev [mailto:llvm-dev-bounces@lists.llvm.org]
<b>On Behalf Of </b>Charith Mendis via llvm-dev<br>
<b>Sent:</b> Saturday, October 29, 2016 00:26<br>
<b>To:</b> llvm-dev <llvm-dev@lists.llvm.org><br>
<b>Subject:</b> [llvm-dev] Vector Shuffle chain lowering to X86 instructions simplification inconsistencies<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Hi all,<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Attached herewith is a fairly simple LLVM file (shuffle.ll) with lots of vector shuffles. <o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">When I use llc with -O3 -mcpu=core-avx2 the first shuffle sequence containing types of 128 wide gets reduced a single shuffle, where as the second shuffle sequence containing types of 256 wide doesn't get reduced to a single shuffle instruction
in the resulting X86 code (Shuffle.s attached).<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">The second sequence is identical to first and is a rewidening of the sequence for a higher vector length.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Can this be explained and where in the machine lowering passes does this simplification happen?<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Thanks<br clear="all">
<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">-- <o:p></o:p></p>
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<p class="MsoNormal">Kind regards,<br>
Charith Mendis<br>
<br>
Graduate Student,<o:p></o:p></p>
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<p class="MsoNormal">CSAIL,<o:p></o:p></p>
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<p class="MsoNormal">Massachusetts Institute of Technology<o:p></o:p></p>
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