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<div>Spills created at the end of the block (I assume you mean what fast regalloc does at -O0) are created long after instruction selection. In that case it sounds like your implementation of storeRegToStackSlot/loadRegFromStackSlot is broken</div>
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<div>-Matt<br>
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<div class="x_gmail_quote">On Tue, Oct 25, 2016 at 7:30 AM +0800, "Alex Susu via llvm-dev"
<span dir="ltr"><<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>></span> wrote:<br>
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<div class="PlainText"> Hello.<br>
I have extended the BPF back end with vector registers (inspiring from Mips MSA) -
<br>
something like this:<br>
def MSA128D: RegisterClass<"Connex", [v128i16], 32,<br>
(sequence "Wh%u", 0, 31)>;<br>
I also added vector store and load instructions in the style of Mips MSA - see
<br>
<a href="https://github.com/llvm-mirror/llvm/blob/master/lib/Target/Mips/MipsMSAInstrInfo.td">https://github.com/llvm-mirror/llvm/blob/master/lib/Target/Mips/MipsMSAInstrInfo.td</a>, look
<br>
for "def ST_D", etc.<br>
Note however that my vector unit has a separate memory space. This is why I defined
<br>
the vector store like:<br>
class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,<br>
ValueType TyNode, RegisterOperand ROWD,<br>
Operand MemOpnd = uimm4_ptr, ImmLeaf Addr = immLeafAlex,<br>
InstrItinClass itin = NoItinerary> {<br>
dag OutOperandList = (outs);<br>
dag InOperandList = (ins ROWD:$wd, MemOpnd:$addrdst);<br>
string AsmString = !strconcat("LS[$addrdst] = $wd;",<br>
instr_asm);<br>
list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addrdst)];<br>
InstrItinClass Itinerary = itin;<br>
string DecoderMethod = "DecodeMSA128Mem";<br>
}<br>
<br>
Also, BPF has its own scalar stores and loads (with the standard i64 registers), for
<br>
example (from <a href="https://github.com/llvm-mirror/llvm/blob/master/lib/Target/BPF/BPFInstrInfo.td):">
https://github.com/llvm-mirror/llvm/blob/master/lib/Target/BPF/BPFInstrInfo.td):</a><br>
class STOREi64<bits<2> Opc, string OpcodeStr, PatFrag OpNode><br>
: STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;<br>
<br>
However, spills and loads with vector registers, created automatically at the border
<br>
of basic-blocks use the scalar stores and loads and NOT the vector ones that are also
<br>
defined. For example, I obtain this ASM code when compiling with my LLVM:<br>
std -512(r10), R(0)<br>
; end of predecessor BB<br>
...<br>
<br>
; beginning of current BB<br>
ldd R(0), -512(r10)<br>
<br>
As we can see STOREi64 takes i64 scalar register normally, but it confuses a v128i16
<br>
register R(0) with an i64 scalar one (r0-r31)...<br>
<br>
Could you please tell me if there is an easy way to fix this? I guess the problem is
<br>
related to the fact the vector unit has its own memory space and I guess LLVM spills
<br>
normally registers on the stack - if so can I specify a different spill region for the
<br>
vector register?<br>
<br>
Thank you,<br>
Alex<br>
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