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</o:shapelayout></xml><![endif]--></head><body lang=EN-IE link="#0563C1" vlink="#954F72"><div class=WordSection1><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'>Anybody got any ideas about this? Implementing FP64 support on a system with no native FP64 capabilities?<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'>I would have expected that it was more-or-less like supporting INT64 on a system that only natively supported INT32, where the compiler abstracts the INT64 into a pair of?<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'>I am seeing the ‘</span><span style='font-size:12.0pt;font-family:"Courier New";color:black'>compiler-rt</span><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'>’ support library functions being called for fundamental operations such as ADD-FP64 and DIV-FP64 using a pair of INT32s, but simple assignment appears to want to allocate physical FP64 registers! Is this a bug?<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'>Other than specifying that the </span><span style='font-size:12.0pt;font-family:"Courier New";color:black'>DataLayout</span><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:black'> </span><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'>is 64-bit size and 64-bit alignment (‘</span><span style='font-size:12.0pt;font-family:"Courier New";color:black'>-f64:64</span><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'>’), and that ‘</span><span style='font-size:12.0pt;font-family:"Courier New";color:black'>long double</span><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'>’ is IEEEdouble, I have not said anything else about FP64, expecting the compiler to fall-back on a default Compiler-RT supported implementation. I have the following specified in ‘</span><span style='font-size:12.0pt;font-family:"Courier New";color:black'>Targets.cpp</span><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'>’:<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'><o:p> </o:p></span></p><p class=MsoNormal style='margin-left:36.0pt'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>LongDoubleWidth = 64u;<o:p></o:p></span></p><p class=MsoNormal style='margin-left:36.0pt'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>LongDoubleAlign = 64u;<o:p></o:p></span></p><p class=MsoNormal style='margin-left:36.0pt'><span style='font-size:12.0pt;font-family:"Courier New";color:black'>LongDoubleFormat = &llvm::APFloat::IEEEdouble;<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'>It seems odd that the compiler falls back on a 2 x INT32 representation for most things (add, sub, div, mul, fp64-int, int-fp64, etc.), but not simple assignment.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'>When we implemented INT64 on our INT32 architecture, we originally accepted the default 2 x INT32 solution that compiler provided where there were no INT64 registers. This was fine, except for efficiency. Later we added an ‘</span><span style='font-size:12.0pt;font-family:"Courier New";color:black'>i64</span><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'>’ register class hoping to be able to make Load/Store legal, but unfortunately this had the unexpected impact of us also having to provide lowering solutions for things that ‘</span><span style='font-size:12.0pt;font-family:"Courier New";color:black'>compiler-rt</span><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'>’ was already doing perfectly well. But I am nervous of having to face the more complex requirement to re-implement as “lowering” specialisations ,those things that ‘</span><span style='font-size:12.0pt;font-family:"Courier New";color:black'>compiler-rt</span><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'>’ already does perfectly well for FP64.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'>Thanks,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'> MartinO <o:p></o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;font-family:"Book Antiqua",serif;color:#943634'><o:p> </o:p></span></p><div><div style='border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0cm 0cm 0cm'><p class=MsoNormal><b><span lang=EN-US style='mso-fareast-language:EN-IE'>From:</span></b><span lang=EN-US style='mso-fareast-language:EN-IE'> Martin J. O'Riordan [mailto:martin.oriordan@movidius.com] <br><b>Sent:</b> 29 September 2016 11:39<br><b>To:</b> 'LLVM Developers' <llvm-dev@lists.llvm.org><br><b>Subject:</b> Register classes and FP64 on target with no FP64 support<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><span lang=EN-GB style='font-size:12.0pt;font-family:"Book Antiqua",serif'>Hi LLVM-Dev,<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-GB style='font-size:12.0pt;font-family:"Book Antiqua",serif'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-GB style='font-size:12.0pt;font-family:"Book Antiqua",serif'>I am trying to implement support for emulated FP64 on our target. Many operations work fine, invoking the appropriate helper function in ‘</span><span lang=EN-GB style='font-size:12.0pt;font-family:"Courier New"'>compiler-rt</span><span lang=EN-GB style='font-size:12.0pt;font-family:"Book Antiqua",serif'>’. But we don’t have a specific register class for FP64 and LLVM usually selects a pair of 32-bit integers, which is fine. The problem is that it doesn’t “always” select a pair of 32-bit integers, and then I get an assertion in ‘</span><span lang=EN-GB style='font-size:12.0pt;font-family:"Courier New"'>TargetRegisterInfo::getMinimalPhysRegClass</span><span lang=EN-GB style='font-size:12.0pt;font-family:"Book Antiqua",serif'>’ that says “Couldn’t find the register class”.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-GB style='font-size:12.0pt;font-family:"Book Antiqua",serif'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-GB style='font-size:12.0pt;font-family:"Book Antiqua",serif'>The funny thing is that something like ‘</span><span lang=EN-GB style='font-size:12.0pt;font-family:"Courier New"'>a = b * c;</span><span lang=EN-GB style='font-size:12.0pt;font-family:"Book Antiqua",serif'>’ works perfectly, but the much simple ‘</span><span lang=EN-GB style='font-size:12.0pt;font-family:"Courier New"'>a = b;</span><span lang=EN-GB style='font-size:12.0pt;font-family:"Book Antiqua",serif'>’ causes this assertion.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-GB style='font-size:12.0pt;font-family:"Book Antiqua",serif'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-GB style='font-size:12.0pt;font-family:"Book Antiqua",serif'>We have not used ‘</span><span lang=EN-GB style='font-size:12.0pt;font-family:"Courier New"'>setOperationAction</span><span lang=EN-GB style='font-size:12.0pt;font-family:"Book Antiqua",serif'>’ for any of the FP64 operations, nor have we created a special register class for them either, in the expectation that it would just reduce to the underlying integers and ‘</span><span lang=EN-GB style='font-size:12.0pt;font-family:"Courier New"'>compiler-rt</span><span lang=EN-GB style='font-size:12.0pt;font-family:"Book Antiqua",serif'>’ calls.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-GB style='font-size:12.0pt;font-family:"Book Antiqua",serif'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-GB style='font-size:12.0pt;font-family:"Book Antiqua",serif'>I’m a bit stumped, so does anyone have any advice about how I should describe our target so that it supports emulated FP64 using either a pair of 32-bit integers or a single 64-bit register as the underlying implementation type?<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-GB style='font-size:12.0pt;font-family:"Book Antiqua",serif'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-GB style='font-size:12.0pt;font-family:"Book Antiqua",serif'>Thanks,<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-GB style='font-size:12.0pt;font-family:"Book Antiqua",serif'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-GB style='font-size:12.0pt;font-family:"Book Antiqua",serif'> MartinO - Movidius<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-GB style='font-size:12.0pt;font-family:"Book Antiqua",serif'><o:p> </o:p></span></p></div></body></html>