<div dir="ltr">Hi,<div><br></div><div>I've been looking at this myself for ARM, and came up with a much simpler solution: lower immediate materializations to a post-RA pseudo and expand the chain of materialization instructions after register allocation / remat. Remat only sees one instruction with no dependencies.</div><div><br></div><div>Did you look down this route and discount it?</div><div><br></div><div>Cheers,</div><div><br></div><div>James</div></div><br><div class="gmail_quote"><div dir="ltr">On Wed, 14 Sep 2016 at 02:43 Gerolf Hoflehner via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style="word-wrap:break-word"><div><blockquote type="cite"><div>On Sep 12, 2016, at 10:14 AM, Andrew Trick via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>> wrote:</div><br><div><div style="word-wrap:break-word"><br><div><blockquote type="cite"><div>On Sep 12, 2016, at 8:51 AM, vivek pandya via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>> wrote:</div><br><div><div dir="ltr"><div><br></div><div>1 ) As LLVM MI is already in SSA form before reg allocation so for LLVM I think it does not require to build SSA graph and converting it back after optimization completed as mentioned in [1]</div><div><br></div><div>2 ) We would like to add a pass similar to SCCP.cpp (Sparse Conditional Constant</div><div>Propagation based on Wegman and Zadeck's work <a href="http://dl.acm.org/citation.cfm?id=103136" target="_blank">http://dl.acm.org/citation.cfm?id=103136</a>) as desribed in [1]. This pass will be scheduled to run before register allocation.</div><div><br></div><div>3 ) Output of the pass added in Step 2 will be a Map of def to instructions pointers (instructions which can be used to remat the given live range). The map will contain live ranges which is due to single instruction and multiple instructions.</div></div></div></blockquote><div><br></div>LiveIntervals maintains a quasi-SSA form via VNInfo. It does not allow efficient def-use queries, but use-def is there, which is all that you should need.</div></div></div></blockquote><div><br></div></div></div><div style="word-wrap:break-word"><div>I also only see a narrow and specific remat cost problem in the example: is it cheaper is issue a chain of instructions rather than a fill? And for this a use-def is sufficient.</div></div><div style="word-wrap:break-word"><div><br><blockquote type="cite"><div><div style="word-wrap:break-word"><div><br></div><div>It would be great to have better remat during regalloc, but please try to avoid building additional state that needs to be maintained.</div></div></div></blockquote><div><br></div></div></div><div style="word-wrap:break-word"><div>You proposed a fairly complex scheme. The question then is always is it worth it? To answer that question you would need to investigate and break down the current remat problems (spills but should remat, remat but should spill, should remat at a different location, etc) eg. for the llvm test suite, and show that your algorithms solves the most important ones.</div></div><div style="word-wrap:break-word"><div><br><div><br></div><br><blockquote type="cite"><div><div style="word-wrap:break-word"><div><br></div><div>-Andy</div><div><br><blockquote type="cite"><div><div dir="ltr"><div><br></div><div>4 ) The remat APIs defined in LiveRangeEdit.cpp will use analysis from the Map</div><div>when a spill is required for RA.</div><div><br></div><div>5 ) The remat transformation APIs like rematerializeAt() will be teached to remat</div><div>live ranges with multiple instructions too.</div><div><br></div><div>6 ) A cost analysis will be require to decide between remat and spill. This should be based on at least two factors register pressure and spill cost</div><div><br></div><div>Few points:</div><div>--------------</div><div>* The analysis pass to be addes as per (2) will use target specific information</div><div>from TargetInstrInfo.cpp as the current remat infrastructure uses.</div><div><br></div><div>* This approach will not be on demand as the current approach is (i.e remat specific</div><div>code will be executed only if there is a spill) so the pass in (2) can be an</div><div>overhead so we may want it to enable only for higher level of optimization.</div><div><br></div><div>* Will it be possible to use existing SCCP.cpp code with few modification to lattice</div><div>and related mathematical operation so that it can serve both purpose?</div><div><br></div><div>* No changes in current register allocators or spill framework will be required</div><div>because remat entry point will be LiveRangeEdit.</div><div><br></div><div>Any other way with less overhead is always welcomed.</div><div>Please help us developing a plan to implement this.</div><div><br></div><div>Hoping for comments!</div><div><br></div><div>Sincerely,</div><div>Vivek</div><div><br></div></div>
_______________________________________________<br>LLVM Developers mailing list<br><a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a><br><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev" target="_blank">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev</a><br></div></blockquote></div><br></div>_______________________________________________<br>LLVM Developers mailing list<br><a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a><br><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev" target="_blank">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev</a><br></div></blockquote></div></div>_______________________________________________<br>
LLVM Developers mailing list<br>
<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a><br>
<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev</a><br>
</blockquote></div>