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    <div class="moz-cite-prefix">On 08/17/2016 09:00 AM, Mehdi Amini via
      llvm-dev wrote:<br>
    </div>
    <blockquote
      cite="mid:4F619BD4-4B23-4310-898A-08AD5E7B74AE@apple.com"
      type="cite">
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          <div class="">On Aug 17, 2016, at 8:49 AM, Hal Finkel via
            llvm-dev <<a moz-do-not-send="true"
              href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a>>
            wrote:</div>
          <br class="Apple-interchange-newline">
          <div class=""><span style="font-family: Helvetica; font-size:
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              inline !important;" class="">----- Original Message -----</span><br
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            <blockquote type="cite" style="font-family: Helvetica;
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              -webkit-text-stroke-width: 0px;" class="">From: "Alex
              Bradbury via llvm-dev" <<a moz-do-not-send="true"
                href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a>><br
                class="">
              To: "llvm-dev" <<a moz-do-not-send="true"
                href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a>><br
                class="">
              Sent: Wednesday, August 17, 2016 4:14:38 AM<br class="">
              Subject: [llvm-dev] [RFC] RISC-V backend<br class="">
              <br class="">
              Hi all,<br class="">
              <br class="">
              I am proposing the integration of a backend targeting the
              RISC-V ISA.<br class="">
              <br class="">
              RISC-V is a free and open instruction set architecture
              that was<br class="">
              originally<br class="">
              developed at UC Berkeley. Future development of the ISA
              specification<br class="">
              will be<br class="">
              handled by the 501(c)(6) non-profit RISC-V Foundation and
              its members<br class="">
              <<a moz-do-not-send="true"
                href="https://riscv.org/membership/?action=viewlistings"
                class="">https://riscv.org/membership/?action=viewlistings</a>>.
              You can find<br class="">
              much more<br class="">
              information at the RISC-V website <<a
                moz-do-not-send="true" href="https://riscv.org/"
                class="">https://riscv.org/</a>>, including the<br
                class="">
              current<br class="">
              ISA specification <<a moz-do-not-send="true"
                href="https://riscv.org/specifications/" class="">https://riscv.org/specifications/</a>>.
              You might note<br class="">
              that<br class="">
              RISC-V defines 32-bit and 64-bit variants and also
              supports a<br class="">
              compressed<br class="">
              variant, allowing 16-bit instructions to be freely
              intermingled with<br class="">
              the<br class="">
              standard 32-bit representations. The standard is
              structured to allow<br class="">
              implementers to choose appropriate subsets to support, for
              instance a<br class="">
              micro-controller might support 'RV32I' (32-bit RISC-V with
              the<br class="">
              integer<br class="">
              instructions) and an application core running Linux might
              implement<br class="">
              RV64IMAFD<br class="">
              (commonly shortened to RV64G: 64-bit with integer
              instructions, the<br class="">
              multiply<br class="">
              extension, atomics, and single and double precision
              floating point).<br class="">
              A<br class="">
              generous portion of the opcode space is left reserved for<br
                class="">
              implementers or<br class="">
              researchers to add their own instructions.<br class="">
              <br class="">
              In line with the proposed policy for adding a new target<br
                class="">
              (<a moz-do-not-send="true"
                href="https://reviews.llvm.org/D23162" class="">https://reviews.llvm.org/D23162</a>),
              RISC-V has a clear specification,<br class="">
              multiple<br class="">
              software models, and multiple FPGA implementations as well
              as<br class="">
              prototype ASICs<br class="">
              from various groups. At lowRISC (<a moz-do-not-send="true"
                href="http://www.lowrisc.org/" class="">http://www.lowrisc.org/</a>),
              inspired<br class="">
              by our<br class="">
              previous experience with the Raspberry Pi project, we are
              working<br class="">
              towards<br class="">
              creating a completely open source RISC-V SoC and producing
              low-cost<br class="">
              development boards around it. Feel free to contact me
              off-list to<br class="">
              discuss<br class="">
              lowRISC further. LLVM is a key part of our development
              plan, and with<br class="">
              community approval I would like to act as maintainer for
              the backend.<br class="">
              The vast<br class="">
              majority of my LLVM work over the past 6 years has sadly
              been<br class="">
              out-of-tree, but<br class="">
              I'm far from new to the project.<br class="">
              <br class="">
              In the RISC-V community right now, GCC is by some way the
              more stable<br class="">
              compiler<br class="">
              port. We've discussed best way of moving forward with LLVM
              at the<br class="">
              last couple<br class="">
              of RISC-V Workshops and a number of us concluded a fresh
              codebase may<br class="">
              be the<br class="">
              best way to move forwards. Producing a series of patches
              that<br class="">
              introduce RISC-V<br class="">
              support incrementally in easy-to-review chunks with
              associated test<br class="">
              cases at<br class="">
              every point also allows us to get the maximum benefit from
              LLVM's<br class="">
              code review<br class="">
              procedure.<br class="">
            </blockquote>
            <br style="font-family: Helvetica; font-size: 12px;
              font-style: normal; font-variant-caps: normal;
              font-weight: normal; letter-spacing: normal; orphans:
              auto; text-align: start; text-indent: 0px; text-transform:
              none; white-space: normal; widows: auto; word-spacing:
              0px; -webkit-text-stroke-width: 0px;" class="">
            <span style="font-family: Helvetica; font-size: 12px;
              font-style: normal; font-variant-caps: normal;
              font-weight: normal; letter-spacing: normal; orphans:
              auto; text-align: start; text-indent: 0px; text-transform:
              none; white-space: normal; widows: auto; word-spacing:
              0px; -webkit-text-stroke-width: 0px; float: none; display:
              inline !important;" class="">Yes, this is exactly the
              process we should follow when practical. I'm in favor of
              this effort.</span><br style="font-family: Helvetica;
              font-size: 12px; font-style: normal; font-variant-caps:
              normal; font-weight: normal; letter-spacing: normal;
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              class="">
          </div>
        </blockquote>
        <div><br class="">
        </div>
        <div>+1</div>
        <div><br class="">
        </div>
        <div>Thanks Alex!</div>
        <div><br class="">
        </div>
      </div>
    </blockquote>
    +1 from me too.  That may have been obvious from my reviews, but
    figured it didn't hurt to say explicitly.  :)<br>
    <blockquote
      cite="mid:4F619BD4-4B23-4310-898A-08AD5E7B74AE@apple.com"
      type="cite">
      <div>
        <blockquote type="cite" class="">
          <div class=""><br style="font-family: Helvetica; font-size:
              12px; font-style: normal; font-variant-caps: normal;
              font-weight: normal; letter-spacing: normal; orphans:
              auto; text-align: start; text-indent: 0px; text-transform:
              none; white-space: normal; widows: auto; word-spacing:
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            <br style="font-family: Helvetica; font-size: 12px;
              font-style: normal; font-variant-caps: normal;
              font-weight: normal; letter-spacing: normal; orphans:
              auto; text-align: start; text-indent: 0px; text-transform:
              none; white-space: normal; widows: auto; word-spacing:
              0px; -webkit-text-stroke-width: 0px;" class="">
            <blockquote type="cite" style="font-family: Helvetica;
              font-size: 12px; font-style: normal; font-variant-caps:
              normal; font-weight: normal; letter-spacing: normal;
              orphans: auto; text-align: start; text-indent: 0px;
              text-transform: none; white-space: normal; widows: auto;
              word-spacing: 0px; -webkit-text-size-adjust: auto;
              -webkit-text-stroke-width: 0px;" class="">It also provides
              a good basis for more detailed<br class="">
              documentation on<br class="">
              writing an LLVM backend (and making modifications to an
              existing one,<br class="">
              e.g.<br class="">
              making it much easier for a research group wanting to
              explore RISC-V<br class="">
              changes).<br class="">
              This is an area I also hope to contribute to. The approach
              of small,<br class="">
              incremental patches is somewhat similar to what is being
              done with<br class="">
              the AVR<br class="">
              backend. I'm grateful to David Chisnall who suggested that
              starting<br class="">
              with the<br class="">
              MC layer may be a productive way to go about developing
              this backend,<br class="">
              and so<br class="">
              far this seems to be working well.<br class="">
              <br class="">
              The current status is that I have submitted a series of 10
              patches<br class="">
              implementing assembler support and an initial set of
              relocations and<br class="">
              fixups.<br class="">
              Help reviewing these would be very welcome, do let me know
              if you'd<br class="">
              like to be<br class="">
              CCed in or added as a reviewer to future patches. I'd
              ultimately like<br class="">
              the<br class="">
              RISC-V backend to be considered a "reference" backend, and
              as such<br class="">
              I specifically welcome reviews you might worry are
              pedantic.<br class="">
              <br class="">
              Please find the current set of patches for your review
              here:<br class="">
              * <<a moz-do-not-send="true"
                href="https://reviews.llvm.org/differential/?authors=asb"
                class="">https://reviews.llvm.org/differential/?authors=asb</a>><br
                class="">
              <br class="">
              I've obviously spent a lot of time with the MC layer
              recently, and<br class="">
              I'd be<br class="">
              happy to put that to use in helping review MC patches for
              other<br class="">
              archs.<br class="">
              <br class="">
              Mini development roadmap:<br class="">
              * Complete MC layer (supporting up to RV32+RV64G at least)<br
                class="">
               * There is currently no specification for supported
              RISC-V assembly<br class="">
               syntax,<br class="">
               mnemonics etc. The ideal solution may not always be
              "whatever the<br class="">
               GCC port<br class="">
               currently does", so some aspect of this will involve
              discussions<br class="">
               with the<br class="">
               wider RISC-V software community.<br class="">
              * Codegen<br class="">
              * Compressed instruction set support (RVC)<br class="">
              * Benchmarking and comparison to GCC RISC-V (and
              potentially other<br class="">
              archs)<br class="">
              <br class="">
              Finally I'd like to give a prominent mention to Colin
              Schmidt, the UC<br class="">
              Berkeley<br class="">
              student who has been maintaining the current out-of-tree
              RISC-V LLVM<br class="">
              port<br class="">
              <<a moz-do-not-send="true"
                href="https://github.com/riscv/riscv-llvm" class="">https://github.com/riscv/riscv-llvm</a>>.
              The RISC-V community owes him<br class="">
              a debt of<br class="">
              gratitude.<br class="">
              <br class="">
              All comments very welcome,<br class="">
              <br class="">
              Alex<br class="">
              _______________________________________________<br
                class="">
              LLVM Developers mailing list<br class="">
              <a moz-do-not-send="true"
                href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a><br
                class="">
              <a class="moz-txt-link-freetext" href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev</a><br
                class="">
              <br class="">
            </blockquote>
            <br style="font-family: Helvetica; font-size: 12px;
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            <span style="font-family: Helvetica; font-size: 12px;
              font-style: normal; font-variant-caps: normal;
              font-weight: normal; letter-spacing: normal; orphans:
              auto; text-align: start; text-indent: 0px; text-transform:
              none; white-space: normal; widows: auto; word-spacing:
              0px; -webkit-text-stroke-width: 0px; float: none; display:
              inline !important;" class="">--<span
                class="Apple-converted-space"> </span></span><br
              style="font-family: Helvetica; font-size: 12px;
              font-style: normal; font-variant-caps: normal;
              font-weight: normal; letter-spacing: normal; orphans:
              auto; text-align: start; text-indent: 0px; text-transform:
              none; white-space: normal; widows: auto; word-spacing:
              0px; -webkit-text-stroke-width: 0px;" class="">
            <span style="font-family: Helvetica; font-size: 12px;
              font-style: normal; font-variant-caps: normal;
              font-weight: normal; letter-spacing: normal; orphans:
              auto; text-align: start; text-indent: 0px; text-transform:
              none; white-space: normal; widows: auto; word-spacing:
              0px; -webkit-text-stroke-width: 0px; float: none; display:
              inline !important;" class="">Hal Finkel</span><br
              style="font-family: Helvetica; font-size: 12px;
              font-style: normal; font-variant-caps: normal;
              font-weight: normal; letter-spacing: normal; orphans:
              auto; text-align: start; text-indent: 0px; text-transform:
              none; white-space: normal; widows: auto; word-spacing:
              0px; -webkit-text-stroke-width: 0px;" class="">
            <span style="font-family: Helvetica; font-size: 12px;
              font-style: normal; font-variant-caps: normal;
              font-weight: normal; letter-spacing: normal; orphans:
              auto; text-align: start; text-indent: 0px; text-transform:
              none; white-space: normal; widows: auto; word-spacing:
              0px; -webkit-text-stroke-width: 0px; float: none; display:
              inline !important;" class="">Assistant Computational
              Scientist</span><br style="font-family: Helvetica;
              font-size: 12px; font-style: normal; font-variant-caps:
              normal; font-weight: normal; letter-spacing: normal;
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              text-transform: none; white-space: normal; widows: auto;
              word-spacing: 0px; -webkit-text-stroke-width: 0px;"
              class="">
            <span style="font-family: Helvetica; font-size: 12px;
              font-style: normal; font-variant-caps: normal;
              font-weight: normal; letter-spacing: normal; orphans:
              auto; text-align: start; text-indent: 0px; text-transform:
              none; white-space: normal; widows: auto; word-spacing:
              0px; -webkit-text-stroke-width: 0px; float: none; display:
              inline !important;" class="">Leadership Computing Facility</span><br
              style="font-family: Helvetica; font-size: 12px;
              font-style: normal; font-variant-caps: normal;
              font-weight: normal; letter-spacing: normal; orphans:
              auto; text-align: start; text-indent: 0px; text-transform:
              none; white-space: normal; widows: auto; word-spacing:
              0px; -webkit-text-stroke-width: 0px;" class="">
            <span style="font-family: Helvetica; font-size: 12px;
              font-style: normal; font-variant-caps: normal;
              font-weight: normal; letter-spacing: normal; orphans:
              auto; text-align: start; text-indent: 0px; text-transform:
              none; white-space: normal; widows: auto; word-spacing:
              0px; -webkit-text-stroke-width: 0px; float: none; display:
              inline !important;" class="">Argonne National Laboratory</span><br
              style="font-family: Helvetica; font-size: 12px;
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              auto; text-align: start; text-indent: 0px; text-transform:
              none; white-space: normal; widows: auto; word-spacing:
              0px; -webkit-text-stroke-width: 0px;" class="">
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              none; white-space: normal; widows: auto; word-spacing:
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              none; white-space: normal; widows: auto; word-spacing:
              0px; -webkit-text-stroke-width: 0px;" class="">
            <span style="font-family: Helvetica; font-size: 12px;
              font-style: normal; font-variant-caps: normal;
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              auto; text-align: start; text-indent: 0px; text-transform:
              none; white-space: normal; widows: auto; word-spacing:
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              href="mailto:llvm-dev@lists.llvm.org" style="font-family:
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              font-variant-caps: normal; font-weight: normal;
              letter-spacing: normal; orphans: auto; text-align: start;
              text-indent: 0px; text-transform: none; white-space:
              normal; widows: auto; word-spacing: 0px;
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              none; white-space: normal; widows: auto; word-spacing:
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      <pre wrap="">_______________________________________________
LLVM Developers mailing list
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</pre>
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